[sv-ec] Re: [sv-ac] SystemVerilog 3.1A Errata And IEEE P1800 Activities

 
 
I recommend that we clarify the followingstatement in 17.6, as it cause a
lot of confusion when we were discussing in in the verification guild.
 

 
Change FROM
2. LRM Section 17.6 Declaring Sequences
...A sequence can be declared with optional formal arguments...
..
-upper range as $
TO:
-upper range as $ or a static natural number.
 
Justification: Confusion on the interretation of the "upper range as $".
ref:
_http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=490&postdays=0&postorder=asc&start=0_
(http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=490&postdays=0&postorder=asc&start=0)
and the question " Question2: Can the delay range be dynamic using a
variable, like ##[5:w]
My thoughts: NO. The range must be known at compile time, like ##[0:5], or
##[0:$] "
with the answer, based on 17.6 " This actually seems to be saying that you
the answer is YES, since I could have written a $ for the upper range in my
example. "
 
As you can see, thos is an area that created confusion, and the LRM needs to
clarify this point.
Thanks,
Ben

 
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Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
_http://www.vhdlcohen.com/_ (http://www.vhdlcohen.com/) vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004 isbn
 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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Received on Fri Jul 2 17:05:21 2004