Greetings,
I believe this should be handled in SV-AC since it is related to Section 17 and assertions.
Regards
David
-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Wolfgang.Ecker@infineon.com
Sent: Thursday, April 22, 2004 9:16 AM
To: sv-ec@eda.org
Subject: [sv-ec] Comments to SystemVerilog_3.1a_draft6_clean Section 17 Assertions.doc
Resent to sv-ec, due to mail problems
> -----Ursprüngliche Nachricht-----
> Von: Ecker Wolfgang (CL DAT TI MF)
> Gesendet: Donnerstag, 22. April 2004 18:12
> An: sv-ac@eda.org; 'sv-ev@eda.org'
> Cc: Gerousis Vassilios (CL DAT CS); Kruse Thomas (CL DAT DF V); Jensen Peter (CL DAT TDM VM external)
> Betreff: Comments to SystemVerilog_3.1a_draft6_clean Section 17 Assertions.doc
>
> Hi SystemVerilog Folks,
>
> please find attached a summary of comments and improvement proposals to the SystemVerilog
> LRM. Mostly, they result from my study of the assertion chapter (gratulations to the author(s)), some
> items (as inconsisten X,Z mapping) cover also other chapters.
>
> Unfortunately, I cannot attend the phone conference on Monday, because I am in the plane to San Franzisco.
> If you plan a meeting in the evening, please let me know. I offer to discuss the items face to face.
>
>
> Kind regards,
> Wolfgang Ecker
>
>
>
>
>
> > <<Comments to SystemVerilog_3.1a_draft6_clean Section 17 Assertions.doc>>
Received on Mon Apr 26 11:09:24 2004
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