[sv-ec] cast of 4 state to 2 state

There are a number of places in the LRM that refer to
'casting a 4-state value to a 2-state value'.

However, the only description (that I can find) for the value mapping when
casting a 4-state value to a 2-state value is in the INFORMATIVE
introduction
to section 3 Data Types. The last sentence of the 5th paragraph in this
section
states:
"To convert a logic value to a bit, 1 converts to 1, anything else to 0."

This definition should be added to a normative section of the LRM.

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On a related issue, in the 1364 LRM defines division by zero is
defined as producing a result of all 'x's. 
4.1.5 Arithmetic operators, second paragraph: 
... For the division or modulus operators, if the second operand is a zero,
then 
the entire result value shall be x. ...
In SystemVerilog, division with 2-state operands produces a 2-state result.
Does the above definition (2-state cast) imply that the result of division
by zero is all 0's.  It may be more useful to explicitly define this result.
Specifically, for 2-state division by zero if the numerator is:
  - an unsigned 2-state value, the result is all 1's.
  - a non-negative signed 2-state value, the result is 0 followed by all 1's
    (ie largest positive signed value of the specific width).
  - a negative signed 2-state value, the result is 1 followed by all 0's
    (ie largest negative signed value of the specific width).
Ray Ryan