Greetings,
This officially opens the balloting as describe below.
1. Statement:"SV-EC accepts LRM Draft 5 as the SystemVerilog 3.1A standard and recommends forwarding it to the Accellera
board for its approval."
2. Eligible companies: Based on attendance and other Accellera rules, the following companies are eligible to vote:
- Cadence Design Systems
- Mentor Graphics
- Motorola, Inc.
- Sun Microsystems
- Synopsys, Inc.
3. Rules:
1. All rules related to Accellera voting guidelines apply. If there is any conflict between Accellera rules and rules given
below, Accellera rules will take precedence. Accellera TCC reserves the right to decide on any conflict.
2. Only one from each company is allowed. In case of multiple people vote from the same company, only the first vote is
counted.
3. Casting options are (1) YES, (2) NO and (3) ABSTAIN. Any other response will disqualify a vote.
4.
A. This is a CLOSED vote to reduce discussion on the voting itself and to keep privacy of the member companies. Please send your
cast to the chair (dwsmith@synopsys.com) AND the co-chair (Neil.Korpusik@Sun.COM).
B. The result and the voting tally will be made public *after* the voting period is over.
C. In case any member wants to make its voting preference public, they may send the vote to the sv-ec reflector; however, sv-ec
will honor privacy of companies who do not wish to make their choice public during the voting period.
5. The vote closes on 15th March, 2004. The result will be published on 17th March, 2004.
Please note that www.eda.org/sv contains a list of changes (some approved and some proposed) to the LRM. We will review and vote on
the SV-EC changes at next Monday's meeting.
Regards
David
David W. Smith
Synopsys Scientist
Synopsys, Inc.
Synopsys Technology Park
2025 NW Cornelius Pass Road
Hillsboro, OR 97124
Voice: 503.547.6467
Main: 503.547.6000
FAX: 503.547.6906
Email: <mailto:david.smith@synopsys.com> david.smith@synopsys.com
<http://www.synopsys.com> http://www.synopsys.com
Received on Wed Mar 10 17:20:58 2004
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