Subject: [sv-ec] draft 5 Acknowledgement section
From: Neil Korpusik (Neil.Korpusik@Sun.com)
Date: Mon Mar 01 2004 - 15:54:03 PST
Hi David,
I noted the following in SV 3.1a draft 5,
1. Page iii, section Acknowledgements, first item in dashed list, description
of the Basic/Design Committee reads:
"The Basic/Design Committee (SV-BC) worked on errata extensions to the
design features of System Verilog 3.1."
The word "and" should be added so that it becomes:
"The Basic/Design Committee (SV-BC) worked on errata and extensions to the
design features of System Verilog 3.1."
2. Page iii, section Acknowledgements, second item in dashed list, description
of enhancement committee reads:
"The Enhancement Committee (SV-EC) worked on errata and extensions to the
design features of System Verilog 3.1."
This is almost the same description given for the SV-BC. It should be
re-worded to be something like:
"The Enhancement Committee (SV-EC) worked on errata and extensions to the
testbench features of System Verilog 3.1."
Neil
-- --------------------------------------------------------------------- Neil Korpusik Tel: 408-720-4852 Member of Technical Staff Fax: 408-720-4850 Frontend Technologies - ASICs & Processors (FTAP) Sun Microsystems email: neil.korpusik@sun.com ---------------------------------------------------------------------
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