Subject: RE: [sv-ec] Re: SV Failure & final Blocks
From: David W. Smith (dwsmith@synopsys.com)
Date: Fri Feb 27 2004 - 13:02:36 PST
Hi Michael,
Just for the record. Yes, it is too late for any more changes in Draft 5. Hopefully it will be posted today.
If there is a need for any changes then we can discuss them in the meeting on Monday and talk about hoe to handle them.
Regards
David
-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Michael Burns
Sent: Friday, February 27, 2004 12:24 PM
To: R.Slater@motorola.com; sv-ec@eda.org
Subject: [sv-ec] Re: SV Failure & final Blocks
Hi Rob (and committee),
It appears that the final blocks are intended to execute at the end of
simulation, regardless of the reason. Section 8.7 attempts to
enumerate all the possible reasons for the simulation to terminate,
which I think is a mistake. Specifically, I think the following text
in 8.7 should be removed:
"After one of the following conditions occur, all spawned processes
are terminated, all pending PLI callbacks are canceled, and then the
final block executes.
- The event queue is empty
- Execution of $finish
- Termination of all program blocks, which executes an implicit $finish
- PLI execution of tf_dofinish() or vpi_control(vpiFinish,...)"
Perhaps it's not too late to squeeze in another LRM change...
Here's what I think about the situations you list:
(1) $stop -- No - simulation suspends, it doesn't finish.
(2) $finish -- Yes
(3) $exit -- Only on the last $exit - there could be more than one program
block and more than one call to $exit.
(4) $fatal -- Yes
Any opinion from those who are actually implementing simulators?
Mike
>...
>
>I have a question regarding the behavior of final blocks and
>SystemVerilog.
>According to the SystemVerilog LRM 3.1a Draft 4 -- Section 8.7 on page
>88,
>should the simulator run final blocks when the following occur? (The
>remarks
>after the "--" are my guesses.) :
> (1) $stop -- Probably not, and we wouldn't want them to be called
> (2) $finish -- Yes
> (3) $exit -- I think so
> (4) $fatal -- Not clear
>
>The LRM is not clear about this. Could you help clarify this (or
>have Acclera clarify it)?
>
>For the record, we want a way to run some final statements after the
>Simulation has determined something is seriously wrong and needs to
>Bail. This function does not exist today in Verilog (i.e. Verilog-2001)
>but do exist in Vera in the form a Exit Handler. The question is does
>final blocks finally provide a solution in Verilog.
>...
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