Re: [sv-ec] Clarification of 19.4 modports

Subject: Re: [sv-ec] Clarification of 19.4 modports
From: Peter Flake (Peter.Flake@synopsys.com)
Date: Fri Feb 27 2004 - 10:21:06 PST

Hi Mike,

Your second version is correct.  The modport can be specified in either place to restrict access.
To quote draft 4:

Note that if no modport is specified in the module header or in the port connection, then all the nets and variables
in the interface are accessible with direction inout or ref, as in the examples above.

Regards,

Peter.

At 11:42 27/02/2004 -0600, Michael Burns wrote:

Hi folks (especially Arturo - I think this section may be from you),

Is the intent of the last paragraph in 19.4 (reproduced below) this:

  all the nets and variables in the interface are accessible with
  direction inout or ref if *either* 1) no modport is specified in the
  module header, *or* 2) no modport is specified in the port
  connection.

Or is it this:

  all the nets and variables in the interface are accessible with
  direction inout or ref if *both* 1) no modport is specified in the
  module header, *and* 2) no modport is specified in the port
  connection.

The spec seems to say the first (barely), but the second seems to be
more what one would expect.

Mike

------- Start of forwarded message -------
Date: Fri, 27 Feb 2004 11:35:18 -0600 (CST)
To: R.Slater@motorola.com
CC: Michael.Burns@motorola.com
Subject: Re: SystemVerlog 3.1a D 4 Spec Bug
From: Michael Burns <Michael.Burns@motorola.com>
Reply-to: Michael.Burns@motorola.com


Hi Rob,

Sorry for the delay - I've been locked up in meetings for days...

At the very end of the section there's a paragraph that says,

  "Note that if no modport is specified in the module header or in the
  port connection, then all the nets and variables in the interface
  are accessible with direction inout or ref, as in the examples
  above."

To be particularly pedantic: if we logically decompose the above spec,
it would appear to say that all interface signals are available if
*either* 1) no modport is specified in the module header, *or* 2) no
modport is specified in the port connection. Your example specified a
modport in the port connection, but not in the module header, so all
interface signals should be visible.

However, I'm not convinced this was the intent of the committee - it
rests too heavily on the word "or", which could have been chosen
without much though. I'll ask.

Mike

>Mike,
>
>I noticed that in Section 19.4 of the SystemVerlog 3.1a Draft 4,
>discussion on modports, it does not explicitly say that if a port
>is not specified in the modport declaration then it is not exported
>to instantiated modules.
>
>In other words, given:
>interface rw_if
>  logic a;
>  logic b;
>  logic c;
>
>  modport clown (input a,
>                           output b);
>
>endinterface:  rw_if
>
>rw_if rw;
>
>module dodo(rw_if rw);
>  initial
>    rw.c <= 0;  // Should fail because c doesn't exist in this view
>endmodule // dodo
>
>module top;
>  dodo bozo(rw.clown);
>endmodule // top
>
>
>I know this sounds picky, but I've already written an example
>in VCS where it treats undeclared ports as inout rather than
>non-existent as one would expect.
>
>Can you follow up on this?
>
>
>Thanks,
>
>Rob
>
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