Subject: [sv-ec] Notes on draft 4
From: Stefen Boyd (stefen@boyd.com)
Date: Thu Feb 19 2004 - 16:12:57 PST
I had sent these to David and he said they should have
been copied to reflector.
Stefen
Section 2.7:
"The inner pair of braces in a replication is removed."
This seems confusing, since the braces aren't really removed... replication has
always had two sets of braces to do the same thing as a concat.
Perhaps: "The inner pair of braces in a replication do not correspond to
a dimension. They disappear when the replication is expanded."
"typedef int triple [1:3]; // 3 integers packed together"
comment should be "3 integers in unpacked array"
Section 2.8
Same wording issue as 2.7. Braces aren't removed...
Section 3.10.2
Example is wrong for description:
"enum { register[1] = 1, register[2:4] = 10 } vr;
The example above declares enumerated variable vr, which creates the
enumerated labels named constants
register0 and register1, which are assigned the values 1 and 2,
respectively. Next, it creates the enumer-ated
labels named constants register2, register3, and register4, and assigns
them the values 10, 11,
and 12."
If the example is changed to:
"enum { register[2] = 1, register[2:4] = 10 } vr;"
Then it should behave as described.
Section 3.14 (end):
Comment in example should be changed:
Replace: "// tagged defined above"
With: "// tagged_st defined above"
Also, perhaps tagged_st isn't best name since it doesn't
use builtin tag.
Section 4.6.1
"array_identifier = new[size] [(src_array)];"
Seems confusing mixing bnf use of [] and literal []
shouldn't we bold some of these?
"array_identifier = new[size] [(src_array)];"
Section 4.8 second paragraph:
REPLACE:
"If one of dimensions of a formal is unsized, then any size of the
corresponding dimension of an actual is accepted."
WITH:
"If one of dimensions of a formal is unsized, then any size of the
corresponding dimension of an actual is accepted."
Section 4.9 last sentence:
REPLACE:
"Associative arrays elements are unpacked, meaning that other than copying
or comparing
arrays, you must select an individual element out of the array before using
it in most expressions."
WITH:
"Associative arrays elements are unpacked, meaning that other than copying
or comparing
arrays, you must select an individual element out of the array before using
it in most expressions."
Section 4.14.1 bullet list should line up. Some lines are indented more
than others.
Section 4.15 last sentence:
REPLACE:
"In contrast, the with clause used by the randomize method (see Section
12.6) accept a set of constraints enclosed in braces."
WITH:
"In contrast, the with clause used by the randomize method (see Section
12.6) accepts a set of constraints enclosed in braces."
Section 5.1:
Second sentence has bold , which doesn't need to be bold. The one after
genvars.
"Verilog 2001 constants are literals, genvars, parameters, localparams and
specparams."
Section 5.8.1 first paragraph after 8 rules:
I tried to make some tweaks for grammar and clarity:
"The scope of a type identifier equivalence includes the hierarchical
instance scope. This means that each instance with user
defined types declared inside the instance creates a unique type. To have
type equivalence among multiple
instances of the same module, interface, or program, a type must be
declared at a higher level in the compilation
unit scope than the declaration of the module, interface or program, or
imported from a package."
Section 7.11, example at end
This looks like a typo:
"m[1][I] // longest static prefix is m[1]"
I suspect that a lower case i was intended:
"m[1][Ii] // longest static prefix is m[1]"
Section 7.12, sentence after strikeout:
should remove "more" since initializing arrays has been removed from this
section:
"Refer to Sections 2.7 and 2.8 for more information on initializing arrays
and structures ."
Section 7.13, last sentence:
typo:
"If the type key, default key, or replication operator is used on an
expression with side effects, the number of times
that expression evaluates is undefined."
Section 7.14, paragraph before matching rules at bottom:
This is unclear:
"Outside the context of an assignment to an aggregate type, an explicit
cast must
be used with the braces to distinguish it from a concatenation. When the
braces
include a label, type, or default key, the braces shall not be interpreted
as a concatenation for
both packed and unpacked structure types."
I'm not sure, but it looks like the intent was:
"Outside the context of an assignment to an aggregate type, an explicit
cast must
be used with the braces to distinguish it from a concatenation. When the
braces
include a label, type, or default key, the braces shall not be interpreted
as a concatenation for
both packed and unpacked structure types, even when outside the context of
an assignment."
Section 7.14, last sentence:
typo:
"OIf the type key, default key, or replication operator is used on an
expression with side effects, the number of
times that expression evaluates is undefined."
Section 7.15, end of example:
some "tagged" keywords aren't bold:
i1 = tagged Jmp (tagged JmpU 239);
// Create a Jump instruction, with "conditional" sub-opcode
i2 = tagged Jmp (tagged JmpC { 2, 83 }); // inner struct by position
i2 = tagged Jmp (tagged JmpC { cc:2, addr:83 }); // by name
Section 7.17, second paragraph:
This suggests one of two things:
"The overload declaration allows the arithmetic operators to be applied to
data types that are normally illegal
for them, such as unpacked structures. It does not change the meaning of
the operators for those types where it
is legal to apply them. This means that such code does not change behavior
when operator overloading is used."
Either change the above wording or add one more sentence:
1) "It is an error to define an overload for an operator
whose types are already legal, such as 'bind + function int
myadd (int, int);'"
2) "If an overload is defined for an operator whose types
are already legal, that overload will be ignored and a warning
may be generated."
Or change the wording:
"The overload declaration allows the arithmetic operators to be applied to
data types that are normally illegal
for them, such as unpacked structures. It does not change the meaning of
the operators for those types where it
is legal to apply them, and no overload has been defined. This means that
such code does not change behavior
when operator overloading is used."
I believe my first suggested sentence addition captures the meaning
since the fourth paragraph up from the end of 7.17 states:
"Note that the assignment operator from a float to a float cannot be
overloaded here because it is already legal.
Similarly, equality and inequality between floats cannot be overloaded."
Section 7.17, conflict (first one should be struck):
third paragraph, third sentence:
"Multiple functions can have the same arguments and different return types."
conflicts with 5th paragraph (just after bullet list
of expected result types):
"Two functions cannot have the same arguments and different return types.
For example, suppose there is a
structure type float:"
Section 7.17, example uses same function for two binds:
unless this is allowed (using same function for different assignment
compatable types), these should be made unique:
REPLACE:
"bind + function float faddrf(shortreal, float);
bind + function float faddfr(float, real);
bind + function float faddfr(float, shortreal);
...
bind + function float fcopyr(shortreal); // unary +"
WITH:
"bind + function float faddsrf(shortreal, float);
bind + function float faddfr(float, real);
bind + function float faddfsr(float, shortreal);
...
bind + function float fcopysr(shortreal); // unary +"
Section 7.17, 7th paragraph from end:
Looks like it must have meant integral rather than integer... since integer
would be too restrictive:
REPLACE
"The exception is if the actual
argument is an integer type and there is only one prototype with a
corresponding integer argument, the actual is
implicitly cast to the type in the prototype."
WITH:
"The exception is if the actual
argument is an integral er type and there is only one prototype with a
corresponding integral er argument, the actual is
implicitly cast to the type in the prototype."
Section 7.17, example fcopyi:
This doesn't make sense unless either bind could have used "integer"
or this uses integer:
"For example the fcopyi function can
be defined with an int argument:
function float fcopyi (integer i);
float o;
o.sign = i[31];
o.exponent = 0;
o.mantissa = 0;
...
return o;
endfunction"
Section 8.4, fifth paragraph:
This looks like it's more than a suggestion, so wording should
reflect that:
"To nest another if statement within such a series of conditions, a
begin...end block should must be used."
Section 12.10, example:
missing spaces in comments before "state":
REPLACE:
"a.randomize(); // random variables: x, ystate variables: v, w
a.randomize( x ); // random variables: xstate variables: y, v, w
a.randomize( v, w ); // random variables: v, wstate variables: x, y
a.randomize( w, x ); // random variables: w, xstate variables: y, v"
WITH:
"a.randomize(); // random variables: x, y state variables: v, w
a.randomize( x ); // random variables: x state variables: y, v, w
a.randomize( v, w ); // random variables: v, w state variables: x, y
a.randomize( w, x ); // random variables: w, x state variables: y, v"
Section 12.16.3, second paragraph:
awkward, perhaps this will work better:
REPLACE:
"The production associated with the first case-item
expression that matches the case expression is generated."
WITH:
"The production generated is the one associated with the
first case-item expression matching the case expression ."
Section 15.2, first example:
missing '@' for clocking block:
REPLACE:
"clocking ck1 (posedge clk);
default input #1step output negedge; // legal
// outputs driven on the negedge clk
input ... ;
output ... ;
endclocking
clocking ck2 (clk); // no edge specified!
default input #1step output negedge; // legal
input ... ;
output ... ;
endclocking"
WITH:
"clocking ck1 @(posedge clk);
default input #1step output negedge; // legal
// outputs driven on the negedge clk
input ... ;
output ... ;
endclocking
clocking ck2 @(clk); // no edge specified!
default input #1step output negedge; // legal
input ... ;
output ... ;
endclocking"
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