Re: [sv-ec] Conflicting rules in A.2.10 and A.6.5


Subject: Re: [sv-ec] Conflicting rules in A.2.10 and A.6.5
From: Adam Krolnik (krolnik@lsil.com)
Date: Fri Sep 05 2003 - 13:10:32 PDT


Hi Surrendra;

I think we should use a different production rather than event expression.

If we want to support as the value of an actual_arg_expr
   a = posedge clk (1)
   a = b or c or d (2)
   a = b, c, d (3)

Then we should require parenthesis around #2 and #3. One could ask to support
parenthesis around #1 as well to be consistent.

Thus, if one wants a parameter with a default value of changes of signals, they
would write:

sequence tryit (
      a = posedge clk,
      b = (f or g or h)
      );
...

BTW, is it interesting to make a parameter be the change of a set of signals?
Will this sync to the clock controlling the sequence/property/assertion?

      Adam Krolnik
      Verification Mgr.
      LSI Logic Corp.
      Plano TX. 75074
      Co-author "Assertion Based Design"



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