[sv-ec] Blackboxes - Simulation/Language Support

Subject: [sv-ec] Blackboxes - Simulation/Language Support
From: Raghuraman R (raghu@ti.com)
Date: Wed Jun 11 2003 - 01:46:11 PDT

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Hi,

Is it a language restriction that modules cannot be left undefined?

While ATPG tools allow blackboxes, for simulation, it is not straight
forward.

For example,

module TOP;
   ... declarations and definitions ...
   SUBCHIP SUBCHIP_1(.A(net0),.B(net1),.C(net2));
   ... declarations and definitions ...
endmofule

To simulate this with SUBCHIP as blackbox, one has to create an "empty"
module like this

module SUBCHIP(A,B,C);
input A,B;
output C;
endmodule

Can this "empty" module be dispensed off with?

-- 
Regds,
Raghuraman R
ASIC
Texas Instruments (India) Ltd.
Phone : +91-80-5099113
http://www.india.ti.com/~raghu
* Think. *

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