Subject: Re: [sv-ec] Question: logic & reg - what is the difference?
From: Peter Flake (Peter.Flake@synopsys.com)
Date: Thu Jun 05 2003 - 16:20:55 PDT
Hi, Cliff,
I think it is hard to have sensible behavior AND be backward compatible
(including PLI) if they are exactly the same thing.
Peter.
At 15:36 04/06/2003 -0700, Clifford E. Cummings wrote:
>Hi, all -
>
>I was talking to the ModelSim developers and we ran into this question:
>
>Are logic and reg the same thing? Did I miss this proposal and vote?
>
>According to table 3.1, logic has "different use rules from reg."
>
>Section 5.6 - 3rd paragraph
>
>In SystemVerilog, all variables (including reg?) can now be written either
>by one continuous assignment, or by one or more procedural statements,
>including procedural continuous assignments. It shall be an error to have
>multiple continuous assignments or a mixture of procedural and continuous
>assignments writing to the same variable. All data types can write through
>a port.
>
>So now what is the difference between a logic and a reg?
>
>Is logic 100% redundant with reg? Both must be declared.
>
>Regards - Cliff
>----------------------------------------------------
>Cliff Cummings - Sunburst Design, Inc.
>14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
>Phone: 503-641-8446 / FAX: 503-641-8486
>cliffc@sunburst-design.com / www.sunburst-design.com
>Expert Verilog, Synthesis and Verification Training
>
>
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