Subject: Re: FW: [sv-ec] Section 19 of Draft - Interfaces
From: Raghuraman R (raghu@ti.com)
Date: Thu Apr 24 2003 - 20:46:43 PDT
Thanks for the response.
If I want to instantiate not the third-least-significant bit, but say
the second-least-significant bit, does the current standard allow
dummy dummy_inst(.A({,wir1,}), .B(wir2), .Y(wir3));
and one more point is that it mandates the knowledge of bus width. If
one does not want the instantiation to know the bus width, then the
above syntax wont be good enough.
My point is that the syntaxt
dummy dummy_inst(.A[4](wir1), .B(wir2), .Y(wir3));
will work as long as there is a legal A[4].
It could be A[0:4] or A[4:0] or A[4:7] or A[7:4].
There could be an extension to the the above syntax as well in the form of
dummy dummy_inst(.A[4:7]({wir1,wir2,wir3,wir4}),.B(wir5),.C(wir6));
Thanks.
Michael Burns wrote:
> The problem I see with your proposed syntax is that, without looking
> at the port declaration (i.e., without knowing how big the port is or
> how the bits are numbered), you have no idea if you're connecting to
> the MSB of the port, the LSB, some bit in the middle, or even an
> illegal bit (for example, the port declaration could specify a range
> of [7:4]). Right now, I think you can also do this:
>
> wire wir1,wir2,wir3;
> dummy dummy_inst(.A({wir1,,}), .B(wir2), .Y(wir3));
>
> to connect to the third-least-significant bit, though you may have to
> endure compiler warnings about mismatched connection sizes.
>
> Mike Burns
>
>
>>A question sent to the EC reflector that I think BC may also want to answer.
>>
>>Regards
>>David
>>
>>David W. Smith
>>Synopsys Scientist
>>
>>Synopsys, Inc.
>>Synopsys Technology Park
>>2025 NW Cornelius Pass Road
>>Hillsboro, OR 97124
>>
>>Voice: 503.547.6467
>>Main: 503.547.6000
>>FAX: 503.547.6906
>>Email: david.smith@synopsys.com
>>http://www.synopsys.com
>>
>>
>>
>>-----Original Message-----
>>From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
>>Raghuraman R
>>Sent: Wednesday, April 23, 2003 11:11 PM
>>To: sv-ec@eda.org
>>Subject: [sv-ec] Section 19 of Draft - Interfaces
>>
>>
>>Hi,
>>
>>In the module instantiation section, I have this issue.
>>
>>If we are having a module having a port say
>>
>>module dummy (A, B, Y)
>>input [0:3] A;
>>input B;
>>output Y;
>>endmodule
>>
>>and we want to instantiate the module dummy with only bit of the port A
>>instantiated, we need something like this
>>
>>wire wir1,wir2,wir3;
>>dummy dummy_inst(.A[1](wir1), .B(wir2), .Y(wir3));
>>
>>Currently the way to do it is
>>
>>dummy dummy_inst(.A{,wir1,,,},.B(wir2), .Y(wir3));
>>But for this, we have to know the size of the port, but I think with the
>>existing information, one should to be able to instantiate and proceed.
>>
>>Thanks.
>>
>>Thanks.
>>--
>>Regds,
>>
>>Raghuraman R
>>ASIC
>>Texas Instruments (India) Ltd.
>>Phone : +91-80-5099113
>>http://www.india.ti.com/~raghu
>>
>>* Think. *
>
>
>
-- Regds,Raghuraman R ASIC Texas Instruments (India) Ltd. Phone : +91-80-5099113 http://www.india.ti.com/~raghu
* Think. *
This archive was generated by hypermail 2b28 : Thu Apr 24 2003 - 20:50:28 PDT