[sv-ec] RE: Draft 5 LRM issues


Subject: [sv-ec] RE: Draft 5 LRM issues
From: David W. Smith (david.smith@synopsys.com)
Date: Wed Apr 23 2003 - 15:17:18 PDT


Hello Jonathan,
 
Thank you for the comments. The following are some responses to the issues:
 
1. Taken care of in LRM-346
 
2. Your example is not legal. Unpacked array concatenation/slicing uses the
left-hand side (p in the example) to disambiguate the concatenation. In
this particular example, the LHS is a dynamic array of string so only
strings are allowed in the concatenation/slice combination. To accomplish
what you want, a cast would be needed:
 
    p = { d[1:3], "hello", string'( {d[4:5]} ) };
 
3. Appears to be a problem of consistency of definition. This will have to
be worked on in a future change.
4. The question seems to be about what are data types. Looking at the BNF
the list of data_type, for example, does not include sequences, assertions,
random variables, refs, etc... These items are not data types. All of the
items in data_type can be passed but may require the use of a ref. This
could be clarified in a future version as to which require ref and which do
not.
5. Taken care of in LRM-345
6. Taken care of in LRM-345
 
Regards
David
David W. Smith
Synopsys Scientist

Synopsys, Inc.
Synopsys Technology Park
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-----Original Message-----
From: bradford@Synopsys.COM [mailto:bradford@Synopsys.COM] On Behalf Of
Jonathan Bradford;Freiburg
Sent: Wednesday, April 23, 2003 1:59 AM
To: david.smith@Synopsys.COM
Subject: Draft 5 LRM issues

  
Hello David

as a System Verilog observer, here is a quick summary of corrections for
Draft 5,
based on issues I commented on in Draft 4.

[ Hopefully this time the synopsys mailer does not get confused about where
I am from !
i.e. bradford@micronas.com - Micronas is an IC design/manufacturing company
in Freiburg, Germany,
not an EDA company called Synopsys ... ]

Regards

      Jonathan Bradford
  

1) 4.2 Packed and unpacked arrays, p27

from::
System Verilog accepts a single number instead of a range to specify the
size of unpacked arrays

to::
System Verilog also accepts a single number, as an alternative to a range,
to specify the size of unpacked arrays,
  

2) 4.7 Array assignment, p31

p = { d[1:3], "hello", d[4:5] };

The preceding example creates the dynamic array p with contents: "a", "b",
"c", "hello", "d", "e".

- Please add a definition of how the d[4:5] slice could be inserted without
expansion as a single element to form
    e.g. "a", "b", "c", "hello", "de" -> i.e. p = { d[1:3],
"hello", {d[4:5]} }; ?
   otherwise there could remain an ambiguity in dynamic arrays of dynamic
arrays.
  

3) 4.8 Arrays as arguments, p32

   task fun (int a[3:1] [3:1]);

from::
   reg b[3:1][3:1]; // error: incompatible type

to::
   reg b[3:1][3:1]; // OK: Compatible type (assignment compatible) and size.

See 4.7 Array assignment, p30, for definition of assignment compatability.
  

4) 18.1 Introduction, p197

An important enhancement in System Verilog is the ability to pass any data
type through module ports, including nets, and all variable types including
reals, arrays and structures.

- This needs to be extended to be more specific and also define what types
are or are not possible. i.e events, semaphores, mailboxes, class instances,
handles, chandles, refs, random variables, assertions, sequences, properties
etc.
- The same needs to be done for the module parameters.
  

5) 19.5.2 An example using tasks in modports, p223

   module omniMod (interface b);

- interface needs bold

6) 19.5.4 An example of multiple task exports, p225

   task a.Read (input logic
   task a.Write (input logic

- logic needs bold
  
  

-- 

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