Subject: RE: [sv-ec] System include proposal
From: Jay Lawrence (lawrence@cadence.com)
Date: Mon Mar 10 2003 - 09:09:46 PST
I don't think this is a problem, macros can always be used anywhere in
Verilog, the syntax is based on the expansion of a macro not where a
macro can be used. For instance I can say
`define module_name foo
module `module_name;
But the BNF doesn't talk about a macro being used in a module
definition.
Jay
===================================
Jay Lawrence
Architect - Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
> -----Original Message-----
> From: Brad Pierce [mailto:Brad.Pierce@synopsys.com]
> Sent: Monday, March 10, 2003 11:58 AM
> To: sv-ec@eda.org
> Subject: Re: [sv-ec] System include proposal
>
>
> The BNF in this proposal is incomplete, because according to
> section 23.2 --
>
> "The `include directive can be followed by a macro, instead of
> a literal string"
>
> For example,
>
> `define home(filename) `"/home/foo/filename`"
> `include `home(myfile)
>
> -- Brad
>
>
> -----Original Message-----
> From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org]On Behalf Of Jay
> Lawrence
> Sent: Monday, March 10, 2003 4:52 AM
> To: sv-ec@eda.org
> Subject: [sv-ec] System include proposal
>
>
>
> Attached is the proposal on a system-wide include mechanism.
>
> Jay
>
>
>
>
> ===================================
> Jay Lawrence
> Architect - Functional Verification
> Cadence Design Systems, Inc.
> (978) 262-6294
> lawrence@cadence.com
> ===================================
>
>
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