Subject: Re: [sv-ec] Clocking Domains
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Jan 27 2003 - 16:07:35 PST
Another "implicit" signal I'd like to put up for consideration is ".new".
It would be a signal driven with the new signal value when the base signal is about
to be updated by the simulator, i.e. when a write to a value with an associated
.new is descheduled the new implicit is written first. You would be able to use it
to create "preponed" processes for data sampling e.g. for a D-FF:
always @(posdege clock.new) sampled_d = d;
always @(posedge clock) q = sampled_d;
always @(posedge clock) d = new_data;
As with VHDL implicits you would be able to derive another implicit from the implicit
and thereby create multiple phases for verification/synchronization within a delta.
E.g.:
always @(posedge clock.new.new) assert(sampled_d == q);
I'm open to suggestions for another name if "new" seems confusing.
Note the alternative encoding of the block above requires an NBA -
always @(posedge clock) q <= d;
- which hides the scheduling of an event into the next delta and the use of a temporary
variable to hold the scheduled value, so computationally there isn't any extra
overhead in using the ".new" methodology.
Regards,
Kev.
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