Subject: [sv-ec] Re: discrete time
From: dudani@us04.synopsys.com
Date: Wed Jan 15 2003 - 10:22:46 PST
There has been no need to support Verilog events for assertions.
Assertions, as currently defined, satisfy their requirements with the
current notion clocks.
Surrendra
At 12:58 PM 1/14/2003 -0800, you wrote:
> > From Surrendra.Dudani@synopsys.com Tue Jan 14 12:35:56 2003
> >
> > Delta cycles are not quantized, and not part of the language. You cannot
> > refer to a delta cycle.
>
> > Surrendra
>
>What's your definition of "quantized".
>
>We're defining extensions to the language, no reason we can't add counting
>deltas if it makes assertions more usable.
>
>Kev.
>
> > At 12:28 PM 1/14/2003 -0800, you wrote:
> > > > From Surrendra.Dudani@synopsys.com Tue Jan 14 12:19:36 2003
> > > >
> > > > If two events occur within the same time unit, we can refer to their
> > > > occurrence in certain order. However, there is no way to quantify
> the time
> > > > within a time unit. Assertions require quantified time.
> > > > Surrendra
> > >
> > >You can count delta cycles within a tick if you need to. From a logical
> > >standpoint all times are relative, there is no real need to differentiate
> > >between a tick and a delta.
> > >
> > >Kev.
><snip>
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Surrendra A. Dudani
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email: dudani@synopsys.com
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