$sv-ec randomization

Subject: $sv-ec randomization
From: Faisal Haque (fhaque@cisco.com)
Date: Wed Sep 18 2002 - 20:06:56 PDT

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What are the mechanisms implemented to support randomization in SystemVerilog 3.1?
I noticed in yesterday's Vera presentation that the donation does not include constraints or randomization related capabilities.

Random tests and directed random tests require support for constraints and randomization. Without those capabilities the testbench portion of SV will be difficult to use for random tests.

-Faisal

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