FW: VeraLite clarification

Subject: FW: VeraLite clarification
From: David W. Smith (david.smith@synopsys.com)
Date: Tue Sep 03 2002 - 15:27:18 PDT

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I have not seen this show up on the email reflector for SV-EC so I
thought I would resend it.

Regards
David

-----Original Message-----
From: Arturo Salz [mailto:salz@synopsys.COM]
Sent: Tuesday, September 03, 2002 2:51 AM
To: sv-ec@eda.org
Subject: VeraLite clarification

Dear Committee Member,

Please review the attached document containing clarifications to the
test-bench donation to SystemVerilog-3.1. This message is sent on
behalf of Mehdi Mohtashemi from Synopsys. We look forward to meeting
with you all on September 4.

• application/pdf attachment: VeraLite-Clarification.pdf

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