Subject: RE: Data Channels
From: Stuart Swan (stuart@cadence.com)
Date: Thu Jul 25 2002 - 21:49:01 PDT
> BTW, Is there anyone involved in Cadence's VCC tools on this reflector?
> Kev.
Kevin-
I'm indirectly involved in the Cadence's VCC product, but I should
point out that in my experience the "protocol" within discussion
groups as this is to try to keep discussion of specific proprietary tools to
a minimum, and focus on general requirements, approaches to solutions, etc.,
which are "out in the open". So if you have questions, I'll try to answer
them within this context.
Given the current focus of this discussion w.r.t. "data channels" and how
such constructs might be interfaced with C++, I think it is appropriate
to pass along the attached white paper related to SystemC 2.0, since
"channels" are what SystemC 2.0 is all about. Perhaps this might spur
some discussion about how channels in SystemVerilog might be similar
or different, and how channels in SystemVerilog might be interfaced with
C++/SystemC.
If you want still more information about channels in SystemC 2.0, there's
also a book on it:
http://www.systemc.org/projects/sitedocs/document/System_Design_with_SystemC
-Stuart
____________________________________________
Stuart Swan, Senior Architect
System Design Verification Group
Cadence Design Systems
Building 11
2670 Seely Avenue
San Jose, CA 95134
Phone +1 408 895 4579
Email stuart@cadence.com
___________________________________________
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