Subject: Re: Verilog-AMS - Issue 15: `include
From: Paul Graham (pgraham@cadence.com)
Date: Tue Jul 09 2002 - 14:04:50 PDT
> >Actually, 'include' _is_ a reserved word. See Annex B of 1364-2001.
>
> Then Annex B is wrong. I just tested this in Verilog-XL, and it isn't
> reserved. So Mac is right.
I didn't know that Verilog-XL conformed to 1364-2001.
Paul
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