Old postings on packing/alignment


Subject: Old postings on packing/alignment
From: Kevin Cameron (Kevin.Cameron@nsc.com)
Date: Mon Jul 08 2002 - 10:34:38 PDT


Here are some previous posts on data/alignment.
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http://www.eda.org/vlog-pp/hm/0457.html

     Apart from endianess, there is an issue with size of data in unions. The types bit,char,integer etc. are
     as in C, but types like "logic" do not have a defined bit representation - it could be:

      A: an enum (e.g. L0=0,L1=1,LX=2,LZ=3) - requires 2 bits (per node)
      B: value & strength (0,1,X) * (1,Z) - requires 3 bits
      C: value, strength and certainty (0,1) * (1,Z) * (1,X) - also 3 bits, but different coding

     I think it is therfore impossible to sensibly overlay logic and bit types, unions should have
     either all logic or all bit as the base type of all elements. The alternative is to store the
     X & Z orthogonally so that only the bit value is overlayed (using representation C),
     which has performance issues.

     If a union of "structs" is declared, the the fields being overlayed should match in their
     base type (rather than the whole struct).

     [Note: 'logic' and 'reg' should probably be something other than 'integer_type' in the BNF]

http://www.eda.org/vlog-pp/hm/0589.html

     Knowing packing order for data in structures is essential for co-simulating hardware
     and software. It should be possible to define register layout (bit fields) in a C struct
     used by embedded software and have it map consistently to hardware described in
     SystemVerilog.

     Currently I'm simulating a little-endian ARM 7 system on big-endian Sparc machines.
     If SystemVerilog defaulted to big-endian packing of its structures because it was being
     run on Sparc, any mapping I set up between SV structs and C structs will not run the
     same if I then run the simulation on a Linux/X86 simulator.

     SystemVerilog should by default be a simulation platform independent description.

     Previous posts:

     Vlog-pp - Verilog++: Unions - overlaying bits & logic
     Vlog-pp - Verilog++: Re: Unions - overlaying bits & logic

     A secondary issue is whether the X/Z information in logic types is orthogonal to the
     1/0 values, if it is you should be able to create a union of C and SV types such that
     you can extract the C-type 1/0 value, e.g.:

         union {
          int C;
          logic [31:0] SV;
       } csvi;

         ....
         csvi.SV = 32'hDEADBEAF;
         csvi.SV = 32'hXXXXXXXX; // X status of bits is othogonal
         ....
         printf ("0x%08X\n",cvsi.C); // C prints 0xDEADBEEF

     Currently that doesn't appear to be excluded in the LRM, but makes a huge difference
     in how you would approach implementation.

     Previous post:

      Vlog-pp - Verilog++: Integer types in BNF

     There is also no description of how packing "left to right" in System Verilog relates to C packing.

     Note: C distinguishes packed and unpacked with the ':' field syntax, e.g.:

       typedef struct { // packed
             int exp:8,
                 mag:16;
       } exp_mag;

     is not the same as:

      typedef struct { // unpacked
            char exp;
            short mag;
      } exp_mag;

     - "mag" and "exp" will pack differently depending on endianess and whether shorts can be
     byte aligned.

http://www.eda.org/vlog-pp/hm/0591.html

     One aim of SystemVerilog (certainly Superlog) is to remove the use of VPI/PLI
     when integrating C and Verilog. Also, if you are trying to align hardware descriptions
     with embedded code (as with the ARM-7 system I'm currently working on) the C
     code is being executed on the simulated machine (not through PLI/VPI).

     I agree with your statement that the simulator does not have to match the packing of
     any particular C compiler, but I consider it a requirement that I can match the packing
     of most C compilers when necessary. E.g. if I have a bunch of control bits in a memory
     -addressable register I might have the following C-code:

         typedef struct {
         int count:16,
              enable:1;
       } Ctrl;

       const Ctrl *ctrl_reg = (Ctrl *)0x20000;

       ...
       ctrl_reg->count = 10;
       ctrl_reg->enable = 1;

     The layout of "Ctrl" in C will be exact, if I want to reuse that description in SystemVerilog
     I need know which of my 32 bits on the data bus are which in SystemVerilog e.g.:

         union {
         logic [31:0] raw;
         Ctrl ct; // as in C
         ...
       } data; // Bus values
        ...
            case (addr)// Address decode
             32'h20000: if (data.ct.enable) begin
                          x = data.ct.count;
                          ....

     Currently it appears this may work if my target embedded processor uses the
     same alignment and packing as that doing the simulation.

     Ideally, I would add some syntax so that the SystemVerilog version of the struct
     can be derived from the C (like classes in C++) and the alignment added, e.g.:

       struct SV_Ctrl : align (32,little) public Ctrl {}; // match compiled alignment

     Since that kind of addition is too much work for 3.0, we need to define what
     the default packing and alignment is so that the struct can be written to match
     the simulation host instead.

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Kev.



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