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Press ReleaseFor more information contact:Georgia Marszalek Accellera PR Counsel (650) 345-7477 georgia@valleypr.com Accellera Hosts SystemVerilog Symposium and Vendor Fair in Silicon ValleyThursday, December 4, 2003, Santa Clara, Calif.—WhoAccellera, the EDA organization focused on language-based design standards, invites the electronic design community to attend a SystemVerilog Symposium and EDA Vendor Fair in Santa Clara, CaliforniaWhatAccellera's SystemVerilog Symposium features two tracks, lunch and an EDA Vendor FairTrack I: SystemVerilog Basic TrainingSystemVerilog language extensions will be presented in a designer-centric fashion by Verilog design expert, Cliff Cummings of Sunburst Design, Inc. This highly technical event will demonstrate how advanced features of SystemVerilog can now be used to increase design and verification productivity, improve design quality and reduce time-to-market pressures.Track II: SystemVerilog Product Technology TrackThis track is a set of presentations from leading verification suppliers that give in-depth technical insight into how their products leverage the SystemVerilog standard. Topics will include synthesis, assertions, acceleration, emulation, debugging and integration of co-simulation using C-API. Accellera committee members will present updates on current SystemVerilog activities. Lunch will be served during this session. EDA Vendor FairThis is a 2-hour event during which participating companies will demonstrate their SystemVerilog-based products and be available to discuss their SystemVerilog support. Accellera Technical Chair Members will also be available for private discussions. Demos of SystemVerilog-based tools from leading EDA companies including @HDL, Axis Systems, Cadence, Jasper, Mentor Graphics, Novas, Real Intent, Summit Design and Synopsys are featuredWhen8:15am-3: 30pm, Thursday, December 4th, 2003WhereSanta Clara Marriott, 2700 Mission College Blvd., Santa Clara, CA 95054Agenda8:15am - 9:00am - Registration and Continental Breakfast9:00am - 11:30pm - Track I: SystemVerilog Basic Training Track II: SystemVerilog Product Technology Track 11:30am - 1:30pm - Lunch and Accellera SystemVerilog Update 1:30pm - 3:30pm - EDA Vendor Fair Information and RegistrationPlease visit http://www.systemverilog.org/events/sv_symposium03.html for more information, and to register.About SystemVerilogSystemVerilog evolves the Verilog hardware description language (HDL) with powerful design and verification capabilities. It provides design constructs for architectural, algorithmic and transaction-based modeling. It adds an environment for automated testbench generation, while providing assertions to describe design functionality, including complex protocols, to drive verification using simulation or formal verification techniques. Its C-API (Application Programming Interface) provides the ability to mix Verilog and C/C++ constructs.About AccelleraAccellera is an electronics industry organization driving the worldwide development and use of standards required by systems, semiconductor, and design tools companies that enhance a language-based design automation process. For more information, please visit www.accellera.org.Press ContactGeorgia MarszalekAccellera PR Counsel (650) 345-7477 georgia@valleypr.com All trademarks and tradenames are the property of their respective holders. |
