Press Release

Accellera’s HDLCon 2002 Attendance Increases 30%, Proceedings Available
Language-based Electronic Design Conference Attracts Over 600 attendees,--Proceedings Include Best Papers

NAPA, Calif., USA 6 May 2002——Accellera, the EDA organization focused on language-based design standards today announced that this year’s International HDL Conference’s (HDLCon) attendance increased more than 30% over the previous year. In addition, the 2002 Conference Proceedings feature the best papers, and are now available for purchase from Accellera.

Accellera’s annual conference, HDLCon, focuses on hardware description language-based design business and technology practices. It is the ideal forum for obtaining and exchanging innovative HDL design techniques that solve next-generation and system-on-chip (SoC) design challenges. The conference features presentations from executives and technical experts on the strategies and design methods used in language-based design. In addition, HDLcon offers tutorials from the language experts to help designers get the most out of their hardware description languages. More information is available at www.hdlcon.org

According to Dennis Brophy, Accellera’s Chairman, “Accellera’s HDLCon is the premier event to attend. It arms systems and semiconductor companies with the tools to better prepare for the challenges of system-level design and to learn how to accelerate design processes that lead to improved chip functionality and performance.”

Call for Technology
The Accellera ALC group has set a meeting for Tuesday June 27, 2000 to review initial technology contributions. The group believes that no single vendor has all the technology necessary to support next generation system design and by working together, they can develop this next generation at an unprecedented pace. Technology contributions are welcome from all. For information on how to contribute technology to this effort and to confirm attendance at this meeting, please visit www.accellera.org/alc. The meeting is open to all.

Gabe Moretti, General Chair of HDLCon 2002, noted, “Over 600 people attended this year’s conference. Because of the support of our HDLCon 2002 committee members and Accellera’s members and supporters, we were able to offer an outstanding technical program, exhibitor venue and several popular panels and events.”

HDLCon 2002 is sponsored by Accellera and was supported by Axis Systems, Cahners, CMP, Hewlett-Packard, Mentor Graphics, Model Technology, Sun Microsystems and Synopsys.

About the HDLCon 2002 Conference Proceedings and Best Papers
The HDLCon 2002 Proceedings include the best papers selected by the conference attendees, based on their technical merit and value. The Best Paper award was given for "The Facts and Fallacies of Verilog Event Scheduling", Lee Tatischeff, Rohit Rana, Charles Dawson, David Roberts, and the runner-up Best Paper award went to "Adding SUPERLOG Design Assertion Extensions to System Verilog ", Harry Foster, Tom Fitzpatrick, Peter Flake

Honorable mentions were given to the following papers: "New Verilog-2001 Techniques for Creating Parameterized Models", Cliff Cummings "A SystemC GSM Model for Hardware/Software Co-Design", Anup Varma, J.R. Armstrong, James Baker "Using Specman Elite to Verify a 6-Port Switch ASIC", Timothy Holt, Robert Ionta, Tom Franco, Jack Collins "Verilog, the Next Generation: Accellera's SystemVerilog", Stuart Sutherland "Some Personal Thoughts on VHDL 200x", Paul Menchini, Peter Ashendon "Techniques for Designing Efficient Memory Structures for FPGAs from Algorithmic C/C++", Shiv Prakash, Bryan Bowyer

To order the HDLCon 2002 proceedings, visit www.accellera.org/document.html. The cost is $60.00 (USD) plus applicable tax.

About HDLCon 2003
- Please visit http://www.accellera.org/calendar.html to sign up for news about HDLCon 2003 or email www.accellera.org. For a list of Accellera-supported activities, visit http://www.accellera.org/actitivites

Notes to editors
A quote sheet and graphics are available on request.
Acronyms:
DAS - Design Assertion language Subset
EDA - Electronic Design Automation
ESS - Extended Synthesizable Subset
HDL - Hardware Description Language
IEEE - Institute of Electrical and Electronic Engineers
IEEE 1076 - IEEE VHDL standard
IEEE 1364 - IEEE Verilog HDL standard
RTL - Register Transfer Level
VHDL - VHSIC (Very High-Speed IC) HD

For more information about Accellera:
call (408) 358-9510,
fax (408) 358-3910,
e-mail info@accellera.org

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