Press Release

ACCELLERA AND THE IEEE ANNOUNCE APPROVAL AND PUBLICATION OF THE SDF STANDARD: Standard Delay Format is available now as IEEE standard 1497

NAPA, Calif., USA 11 March 2002—Accellera, the EDA organization focused on language-based design standards and the IEEE Standards Association (IEEE-SA) today announced that the Standard Delay Format (SDF) has been approved as IEEE Standard 1497-2001and is now available from the IEEE.

SDF allows for better EDA tools interoperability. It is widely used to communicate timing information and constraints among various EDA tools. It represents and interprets timing data for use at any stage of the electronic design process. ASCII data in the SDF file is represented in a tool and language independent way and includes path delays, timing constraint values, interconnect delays and high-level technology parameters.

“Accellera collaborates with the IEEE, a leading international standards organization to demonstrate our commitment to enhance language-based design,” remarked Dennis Brophy, Accellera chairman, and director of strategic business development at Model Technology, a Mentor Graphics Company. “Because of the important of EDA tool interoperability, SDF has become one of the most important HDL standards used by designers today.”

SDF History
SDF was first introduced into the EDA marketplace in 1991 by Cadence Design Systems, Inc. Cadence placed SDF in the public domain in 1992 when it turned control over to Open Verilog International (OVI), now know as Accellera. Accellera delivered the first SDF standard, version 2.0, in June 1993 (SDF version 1.0 was used by Cadence). Accellera has since introduced version 2.1 in February 1994, and version 3.0 in May 1995. Accellera subsequently turned over the standard to the IEEE that resulted in this standard. In addition to its use with the Verilog HDL, VHDL (IEEE 1076) also takes advantage of SDF through the VITAL standard (IEEE 1076.4). IEEE 1076.4-2001 VITAL specifically references the IEEE 1497-2001 version of the standard.

Price and Availability
The SDF Modeling Standard is available now from the IEEE for $80.00 (USD) or $64.00 (USD) for IEEE members. To order, visit www.ieee.org.

About Accellera
Accellera is an electronics industry organization that drives the worldwide development and use of standards required by systems, semiconductor and design tool companies that enhance a language-based design automation process. This includes support of technical groups involved with developing standards for IEEE 1364 (Verilog HDL) and IEEE 1076 (VHDL). For more information, please visit www.accellera.org. For a list of Accellera-supported activities, visit www.accellera.org/actitivites

About the IEEE Standards Association
The IEEE Standards Association (IEEE-SA) is an international membership organization serving today's industries with a complete portfolio of standards programs. The IEEE-SA is a major contributor to the IEEE, which is the world's largest technical professional society. IEEE-SA membership, through its IEEE association, promotes the engineering process by creating, developing, integrating, sharing and applying knowledge about electro- and information technologies and sciences for the benefit of humanity and the profession. More information is found at http://standards.ieee.org/sa-mem/index.html.

Notes to editors
More information about SDF is at http://www.eda.org/sdf/
Acronyms:
EDA - Electronic Design Automation
ESS - Extended Synthesizable Subset
HDL - Hardware Description Language
IEEE - Institute of Electrical and Electronic Engineers
IEEE 1076 - IEEE VHDL standard
IEEE 1364 - IEEE Verilog HDL standard
SDF - Standard Delay Format
VHDL - VHSIC (Very High-Speed IC) HD

For more information about Accellera:
call (408) 358-9510,
fax (408) 358-3910,
e-mail info@accellera.org

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