Press Release

For more information contact:
Georgia Marszalek
Accellera PR Counsel
(650) 345-7477
georgia@valleypr.com

Accellera Hosts SystemVerilog Symposium and Vendor Fair in Silicon Valley

Thursday, December 4, 2003, Santa Clara, Calif.—

Who

Accellera, the EDA organization focused on language-based design standards, invites the electronic design community to attend a SystemVerilog Symposium and EDA Vendor Fair in Santa Clara, California

What

Accellera's SystemVerilog Symposium features two tracks, lunch and an EDA Vendor Fair

Track I: SystemVerilog Basic Training

SystemVerilog language extensions will be presented in a designer-centric fashion by Verilog design expert, Cliff Cummings of Sunburst Design, Inc. This highly technical event will demonstrate how advanced features of SystemVerilog can now be used to increase design and verification productivity, improve design quality and reduce time-to-market pressures.

Track II: SystemVerilog Product Technology Track

This track is a set of presentations from leading verification suppliers that give in-depth technical insight into how their products leverage the SystemVerilog standard. Topics will include synthesis, assertions, acceleration, emulation, debugging and integration of co-simulation using C-API. Accellera committee members will present updates on current SystemVerilog activities. Lunch will be served during this session.

EDA Vendor Fair

This is a 2-hour event during which participating companies will demonstrate their SystemVerilog-based products and be available to discuss their SystemVerilog support. Accellera Technical Chair Members will also be available for private discussions. Demos of SystemVerilog-based tools from leading EDA companies including @HDL, Axis Systems, Cadence, Jasper, Mentor Graphics, Novas, Real Intent, Summit Design and Synopsys are featured

When

8:15am-3: 30pm, Thursday, December 4th, 2003

Where

Santa Clara Marriott, 2700 Mission College Blvd., Santa Clara, CA 95054

Agenda

8:15am - 9:00am - Registration and Continental Breakfast
9:00am - 11:30pm - Track I: SystemVerilog Basic Training
Track II: SystemVerilog Product Technology Track
11:30am - 1:30pm - Lunch and Accellera SystemVerilog Update
1:30pm - 3:30pm - EDA Vendor Fair

Information and Registration

Please visit http://www.systemverilog.org/events/sv_symposium03.html for more information, and to register.

About SystemVerilog

SystemVerilog evolves the Verilog hardware description language (HDL) with powerful design and verification capabilities. It provides design constructs for architectural, algorithmic and transaction-based modeling. It adds an environment for automated testbench generation, while providing assertions to describe design functionality, including complex protocols, to drive verification using simulation or formal verification techniques. Its C-API (Application Programming Interface) provides the ability to mix Verilog and C/C++ constructs.

About Accellera

Accellera is an electronics industry organization driving the worldwide development and use of standards required by systems, semiconductor, and design tools companies that enhance a language-based design automation process. For more information, please visit www.accellera.org.

Press Contact

Georgia Marszalek
Accellera PR Counsel
(650) 345-7477
georgia@valleypr.com

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