Press Release

For more information contact:
Georgia Marszalek
Accellera PR Counsel
(650) 345-7477
georgia@valleypr.com

Accellera Elects Officers, Announces Plans for Coming Year

October 20, 2003, Napa, Calif.—Accellera, the electronics industry organization focused on language-based design standards, announced today that its corporate members --Axis Systems, Inc., ARM Ltd, Artisan Components, Cadence Design Systems, IBM, Intel Corp., Mentor Graphics, Motorola, NEC, Novas Software, NVIDIA, Real Intent, Sun Microsystems, Synopsys Inc. and Verisity -- have elected officers. In addition, the organization announced plans for the next year, which include sending the Accellera SystemVerilog design language standard to the IEEE for standardization.

Dennis Brophy, director of strategic business development at Model Technology, a Mentor Graphics company, was elected Accellera's chair for a fourth term. Shrenik Mehta, director, Frontend Technologies - ASICs & Processors, Sun Microsystems, was re-elected vice chair. Dave Kelf, vice president of marketing, Novas Software, was elected treasurer. Karen Bartleson, director of interoperability, Synopsys, was re-elected secretary for a fourth term.

"Our members; semiconductor companies, electronic system designers and electronic design automation solution suppliers; work together to create standards that address design complexity and improve the way designers create electronic circuits and systems, and I am pleased to continue as Accellera's chair to help the organization deliver on its goals", remarked Dennis Brophy, Accellera chairman.

Accellera Plans
In the coming year, Accellera plans to enhance the process it uses to build and maintain electronic design standards with the IEEE and assign the copyright of SystemVerilog 3.1a to the IEEE for standardization consideration by the IEEE 1364 Working Group before the 41st Design Automation Conference. Accellera's technical committees have plans in place to complete the unification of Accellera's Property Specification Language (PSL) with SystemVerilog 3.1 assertions to produce PSL 1.1, and synchronize the Accellera Verilog Analog/Mixed Signal (Verilog-AMS) design language standard with its SystemVerilog syntax. Accellera also looks forward to another successful Design Verification Conference in March 2004.

For a list of Accellera-supported activities, please visit http://www.accellera.org/subcom.html. For information on Accellera Design & Verification Conference (DVCon), please visit www.dvcon.com.

About Accellera
Accellera provides design standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA standards that lower the cost of designing commercial IC and EDA products. As a result of Accelleraâs long-standing, successful partnership with the IEEE, Accellera standards are provided to the IEEE standards body for formalization and ongoing change control. For more information about joining Accellera, please visit www.accellera.org.

Notes to editors
Photos available on request.
Acronyms and definition
AMS - Analog Mixed Signal
DVCon - Design & Verification Conference
HDL - Hardware Description Language-Verilog and VHDL
IEEE - Institute of Electrical and Electronic Engineers
IEEE 1364 - Verilog Working Group
PSL - Property Specification Language

Accellera acknowledges trademarks or registered trademarks of other organizations for their respective products and services.