Press Release

Accellera approves FOUR NEW design verification STANDARDS

More about Accellera New Standards
PSL
Accellera's PSL was developed to address the shortcomings of natural language forms of specification. It gives the design architect a standard means of specifying design properties using a concise syntax with clearly defined formal semantics. Similarly, it enables an RTL implementer to capture design intent in a verifiable form, while enabling the verification engineer to validate that the implementation satisfies its specification with dynamic (that is, simulation) and static (that is, formal) verification. It also provides a standard means for hardware designers and verification engineers to rigorously document the design specification.
"A change is taking place in the way we design and verify our designs that will revolutionize the industry and result in the equivalent of a synthesis productivity breakthrough in verification. This change demands that we move from natural language forms of specification to forms that are mathematically precise and verifiable, and lend themselves to automation. The PSL 1.01 standard offers an opportunity to enable this huge leap in productivity of specification, design, and verification," said Harry Foster, Accellera Formal Verification Technical Committee Chair.

SCE-API
The SCE-API standard defines a high-speed, asynchronous, transaction-level interface between simulators or testbenches and hardware-assisted solutions such as emulation or rapid prototypes. "The SCE-API offers an intelligent interface for many types of tools," noted Brian Bailey, Accellera Interfaces Committee Chair. "Since verification requirements are increasing, in many cases, a single tool isn't enough. In these cases, a standard interface between the tools can bring the best in class tools together, and allow for better re-use of models among different design tools."
For more information, please visit http://www.eda.org/itc/.

SystemVerilog
SystemVerilog 3.1 evolves the Verilog language with powerful design and verification capabilities. It provides design constructs for architectural, algorithmic and transaction-based modeling. It adds an environment for automated testbench generation, while providing assertions to describe design functionality, including complex protocols, to drive verification using simulation or formal verification techniques. Its C-API provides the ability to mix Verilog and C/C++ constructs without the need for PLI for direct data exchange. " SystemVerilog 3.1 is a monumental effort that breaks new ground for the electronics industry and nanometer verification challenges,ä said Vassilios Gerousis, Accellera's Technical Committee Chairman. " It is the first hardware design verification language or HDVL standard, built on top of Verilog HDL. It was developed and approved through the cooperation of EDA companies and users alike, with more than 40 worldwide industry experts and 120 contributors."

Gerousis added, "SystemVerilog 3.1 is ready for early adoption by EDA companies and customers."

For more information, please visit the following sites:
SystemVerilog Synthesizable High Level Constructs
SystemVerilog Testbench
SystemVerilog Assertions
SystemVerilog C/API

Verilog-AMS
The Verilog-AMS language standard models mixed-signal behavior. Given the increased mixed-signal content in today's SoCs, the Verilog-AMS language helps to verify a design at the system level as well as at the block level. The 2.1 standard improves the syntax and semantics of the mixed-signal extensions to the Verilog-AMS language making it more intuitive and easier to use. Srikanth Chandrasekaran, Verilog-AMS chair, remarked, "For the next version of Verilog-AMS, we plan to investigate device modeling and RF features. As requested by the Accellera Board, we do plan to synchronize Verilog-AMS more tightly with the digital standards ö SystemVerilog and the IEEE 1364 2001."

For more information, please visit www.eda.org/verilog-ams

About Accellera
Accellera is an electronics industry organization driving the worldwide development and use of standards required by systems, semiconductor, and design tools companies that enhance a language-based design automation process.

Acronyms
AMS - Analog Mixed Signal
EDA - Electronic Design Automation
HDL - Hardware Description Language
IEEE - Institute of Electrical and Electronic Engineers
PLI - Programming Language Interface
PSL - Property Specification Language
RTL - Register Transfer Level
SoC - System on Chip
SCE-API - Standard Co-Emulation Application Programming Interface Accellera acknowledges trademarks or registered trademarks of other organizations for their respective products and services.