Karen Pieper and Johny Srouji Receive Accellera Technical Excellence Award for Contributions to SystemVerilog Standard

SystemVerilog supports architectural & behavioral electronic design & system verification with assertions and testbench

  NAPA, Calif., June 9, 2005, — Accellera, the electronics industry organization focused on electronic design automation standards, has named Synopsys Inc.’s Karen Pieper and IBM’s Johny Srouji the recipients of the organization’s 2nd annual Technical Excellence Award for their contributions to the SystemVerilog hardware description and verification language (HDVL) standard (also known as IEEE P1800). The award is being presented at Accellera’s open Member meeting at the Design Automation Conference (DAC), Wednesday, June 15, 2005 at 10:00am, Anaheim Hilton, Capistrano B. (To attend this meeting, please register at http://www.accellera.org/events/register/.)

  “Karen Pieper and Johny Srouji have been key and instrumental players in the development and delivery of SystemVerilog as a hardware description and verification language standard through both the Accellera and IEEE processes,” noted Dennis Brophy, Accellera chairman. “Their technical leadership in the standardization effort as the Chairs, respectively, of the technical team and the IEEE working group added tremendous value to our SystemVerilog standard.”

About Accellera’s Technical Excellence Award

Accellera’s Technical Excellence Award recognizes major contributions to the development of Accellera’s standards by the organization’s technical committee members. Examples of the contributions may include leadership in standardization of new technologies, assuring achievement of standards development goals or identifying opportunities to better serve the needs of the industry through standards. More Award information is located at www.accellera.org/award.html.

About SystemVerilog & IEEE P1800

The emerging IEEE P1800 standard for SystemVerilog extends the Verilog HDL to provide a unified hardware design, specification and verification language. SystemVerilog includes design specification methods, an embedded assertions language, a testbench language including coverage and assertions, an Application Programming Interface (API), and a Direct Programming Interface (DPI).

  About Accellera’s Technical Excellence Award Recipients

Karen Pieper, Chair of the IEEE P1800 SystemVerilog Technical Sub-Working Group.

Karen Pieper is a R&D Director for Design Compiler at Synopsys. Karen has a Bachelors degree in Computer Science from Rice University, and a PhD. in Computer Science from Stanford University.

Johny Srouji, Chair of IEEE P1800 SystemVerilog Working Group

Johny Srouji works at IBM Austin in the Systems & Technology Group and holds a technical lead position as Power czar in the servers’ microprocessor group. He received his Bachelor and Masters degree in Computer Science from the Technion, Israel Institute of Technology.

About SystemVerilog at the Design Automation Conference, June 13-16

Accellera is sponsoring the SystemVerilog Booth #2284 at the Design Automation Conference next week in Anaheim, California (www.dac.com).

About Accellera

Accellera provides design standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA standards that lower the cost of designing commercial IC and EDA products. As a result of Accellera’s partnership with the IEEE, Accellera standards are provided to the IEEE standards body for formalization and ongoing change control. For more information about Accellera, please visit www.accellera.org.

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Press Contact: Georgia Marszalek, ValleyPR for Accellera, +650 345 7477, Georgia@ValleyPR.com

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