Accellera Participates in SystemVerilog JEITA Meeting at EDS Fair

January 27th, Pacifico, Yokohama, Japan

NAPA, Calif.-- Accellera, the electronics industry organization focused on electronic design automation (EDA) standards, announced today that Accellera members will participate in a SystemVerilog session offered by the Japan Electronic & Information Technology Association’s (JEITA)-- JEITA SV-TG - SystemVerilog User Forum 2005, during EDS Fair.

Date & Time:

Thursday, January 27, 2005

12:30 p.m. to 2:30 p.m.

Location:

        Annex F20x

        Pacifico, Yokohama, Japan

        http://www.pacifico.co.jp/index_e.html

Session Presentations:

        SystemVerilog Standardization Update, Accellera chairman, Dennis Brophy

        IEEE P1800 SystemVerilog Working Group Overview and Update, Oz Levia, Synopsys

        SystemVerilog V3.1a Language Tutorial, Takehiko Tsuchiya, Toshiba Corporation

        SystemVerilog from a User’s Perspective, Stuart Sutherland, Sutherland HDL

More Information:

For more information about EDS Fair, please visit http://www.edsfair.com. For information about the presentation please visit http://www.edsfair.com/systemdesign/.

Admission: Free

About Accellera

Accellera provides design standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA standards that lower the cost of designing commercial IC and EDA products. As a result of Accellera’s partnership with the IEEE, Accellera standards are provided to the IEEE standards body for formalization and ongoing change control. For more information about Accellera, please visit www.accellera.org.

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Press Contact: Georgia Marszalek, ValleyPR for Accellera, 650 345-7477, Georgia@ValleyPR.com

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