Tom Alsop (of Intel) Named Accellera Systems Initiative 2017 Technical Excellence Award Recipient

Alsop will be recognized for his contributions to UVM at DVCon U.S. on February 27, 2017

Elk Grove, Calif., February 22, 2017 -- Accellera Systems Initiative (Accellera) announced today that Tom Alsop, co-chair of the Universal Verification Methodology (UVM) Working Group, is the recipient of the sixth annual Accellera Technical Excellence Award.  The award was established to recognize the outstanding achievements of an individual among Accellera’s working group members and their significant contributions to the development of its standards.

Mr. Alsop will be presented the award at DVCon U.S. on Monday, February 27th during the Accellera Day luncheon from 12:00-1:30pm at the DoubleTree Hotel in San Jose, California.  He will be recognized for his technical contributions and leadership as co-chair of the UVM Working Group and guiding the submission of UVM 1.2 as a contribution to the IEEE P1800.2™ working group for further standardization and maintenance.

“Tom has been a key contributor to the advancement of UVM,” said Karen Pieper, Accellera Technical Committee Chair, “As co-chair of the working group, his leadership has inspired a group of dedicated working group members to work openly to develop the standards policies with well-established flows and processes that have helped make UVM one of the most widely applied standards in the EDA industry.  It is the dedication of leaders like Tom that help to further the advancement of standards that benefit the entire electronics design eco-system.  UVM is a tremendous benefit to the industry, and we have Tom and his team to thank for all of their efforts in getting it to the IEEE.  We are looking forward to his continued success in his new role as chair of the IEEE P1800.2 UVM Working Group.”  

“I am honored to receive this award and recognition from the Accellera members,” said Mr. Alsop, who serves as Principal Engineer at Intel. "I am proud of the UVM Working Group members and their tireless efforts getting the standard to the IEEE.   We have worked very hard on UVM 1.2 and to see it become the basis for IEEE P1800.2 has been incredibly rewarding.  I would like to thank my team for their invaluable contributions.”

Mr. Alsop has been a member and co-chair of the Accellera UVM Working Group for eight years, ultimately forming the IEEE P1800.2 UVM committee and leading UVM to become an IEEE standard in 2017.  The goal of the UVM standard is to improve design productivity by making it easier to verify design components with a standardized representation that can be used with various verification tools, helping to lower verification costs and improve design quality.

Mr. Alsop has spent the last 10 years in the Product Development Solutions team at Intel as a Tool, Flow, and Methodology (TFM) expert supporting RTL and Validation teams across Intel.  He leads Intel’s High Level Synthesis (HLS) efforts and is responsible for the company’s RTL and Validation design infrastructure and environment. He has also made significant contributions to the IEEE 1800 SystemVerilog 2009 and 2012 specifications.

He holds a Bachelor of Science degree in Electrical and Computer Engineering from Brigham Young University. 

About the Accellera Technical Committee
Accellera's Technical Committee oversees 17 working groups that produce effective and efficient Electronic Design Automation (EDA) and Intellectual Property (IP) standards for today's advanced IC designs. Participants include member companies and industry contributors. Technical contributors typically have many years of practical experience with IC design and developing and using EDA tools. For a list of Accellera Working Groups, please click here.

About Accellera Systems Initiative
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit Find out more about membership. Follow @accellera on Twitter or to comment, please use #accellera. Accellera Global Sponsors are:  Cadence, Mentor Graphics and Synopsys.

About DVCon U.S.
DVCon is the premier conference and exhibition for discussion of the functional design and verification of electronic systems. DVCon U.S. is sponsored by Accellera Systems Initiative, an organization focused on the creation and adoption of EDA and IP standards. For more information, please visit For more information about DVCon, please visit Follow @dvcon_us on Twitter or to comment, please use #dvcon_us.

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