Skip Nav
Home » News & Events » Media Coverage

Media Coverage

If you have seen a relevant article not listed below, please let us know.

Media Coverage
Links will open in a new window.
EDA Standards Groups Accellera and OSCI Merge

The increasing challenges of creating complex system-on-chips (SoCs) has brought the need for a single organization like Accellera Systems Initiative to create new IP and EDA standards, Stan Krolikoski added. The focus of Accellera Systems Initiative will continue to be on the standards activities that are under development by both Accellera and OSCI in three areas: systems-level verification, mixed-signal design and verification; and systems-level IP integration.

SemiMD
06 Dec 2011
EDA standards bodies Accellera, OSCI merge

The merged entity, to be known as the Accellera Systems Initiative, is chartered to create comprehensive system-level and semiconductor design standards to benefit the electronic design community by facilitating efficient collaboration among its worldwide members, the organizations said in a statement.

EE Times
05 Dec 2011
Accellera and Open SystemC Initiative (OSCI) Approve Merger, Unite to Form Accellera Systems Initiative

What Others Are Saying: "As Accellera and OSCI come together, we should expect accelerated development and adoption of standards across various ESL domains," said Gary Smith, industry analyst at Gary Smith EDA.

Design & Reuse
05 Dec 2011
Accellera and OSCI Approve Merger and Unite to Form Accellera Systems Initiative

Accellera and the Open SystemC Initiative (OSCI) have announced that their members and Boards have approved their merger, and they have united to form the Accellera Systems Initiative. The new organization leverages the complementary efforts of both organizations and is chartered to create comprehensive system-level and semiconductor design standards to benefit the electronic-design community by facilitating efficient collaboration among its worldwide members.

SoCcentral
05 Dec 2011
Accellera and Open SystemC Initiative (OSCI) Approve Merger, Unite to Form Accellera Systems Initiative

"Our unification and collaborative standards' plans are significant steps that better address the needs of the system and semiconductor design communities worldwide," added OSCI chair Eric Lish. "Accellera Systems Initiative gives our members and stakeholders a better way to improve and extend their SystemC design productivity with industry standards that encompass system-level, RTL and gate-level design flows and IP."

EIN News
05 Dec 2011
Aldec Delivers Complete Support for UVM 1.1, Enabling VMM and OVM Interoperability

The latest release enhances the SystemVerilog verification methodology by providing extended language construct support and adding debugging and productivity features in the waveform. The new language construct enhancements, based on an industry accepted IEEE 1800(TM)-2009 standard, enable customers to do extensive debugging and provide a path to support for UVM together with previous OVM (Open Verification Methodology) and alternative VMM (Verification Methodology Manual) methodologies.

Business Wire
14 Nov 2011
IEEE Approves Revised IEEE 1666 "SystemC Language" Standard for Electronic System-Level Design, Adding Support for Transaction-level Modeling

IEEE, the world's largest professional association advancing technology for humanity, today announced that the IEEE Standards Association (IEEE-SA) Standards Board has approved a revised version of the IEEE 1666 "Standard SystemC Language Reference Manual," which specifies SystemC, the high-level design language used in the design and development of electronic systems. The new version of IEEE 1666 encompasses many enhancements, notably the support for transaction-level modeling (TLM), a critical approach to enable higher level and more efficient design of complex integrated circuits (ICs) and system-on-chips (SoCs).

IEEE Standards Association
10 Nov 2011
Taiwan SystemC Users Group Hosts Third Meeting, November 14-15, 2011

The Open SystemC Initiative (OSCI), an independent non-profit organization dedicated to supporting and advancing SystemC as an industry-standard language for electronic system-level (ESL) design, announces the third meeting of the Taiwan SystemC Users Group to be held November 14-15 at the at the Industrial Technology Research Institute (ITRI) in Hsinchu and the National Cheng Kung University (NCKU) in Tainan, respectively. Sponsored by OSCI, the Taiwan SystemC Users Group Meeting is an industry event where system integrators, modeling experts, EDA suppliers and system-level design and verification architects and engineers can share and exchange knowledge on the industrial application and benefits of using the SystemC language for system-level modeling, design and verification.

EDACafe
07 Nov 2011
Accellera Chair Shishpal Rawat Talks About Roadmap for IP and System Design Standards at IP-SOC 2011

Accellera, the electronics industry organization focused on electronic design automation (EDA) standards, invites IP-SOC 2011 attendees to hear Accellera chair Shishpal Rawat's invited talk on The Roadmap for IP and System Design Standards.

EDACafe
03 Nov 2011
OSCI-Accellera: Cue Mr. Peabody's WABAC Machine

As most of you will have seen by now, Accellera and OSCI have announced the intention to form a new EDA standards organization that will cover the design flow roughly from Gate-level up through the System-level. This may seem to be a natural move to most people, and one that could easily have happened years ago.

"Stan on Standards" Chip Design Blog
23 Jun 2011
EDA Standards Groups Accellera and Open SystemC Initiative will merge

EDA (electronic design automation) standards bodies Accellera and the OSCI (Open SystemC Initiative) have announced their intent to merge into a single organization. The two groups have signed a memorandum of understanding outlining the merger plan, which they say will result in more comprehensive standards that will benefit the worldwide EDA community, and facilitate more efficient collaboration among its members.

EE Daily News
23 Jun 2011
Accellera - OSCI Union: New Synergy for EDA Standards?

According to Stan Krolikoski, group director of standards at Cadence, combining Accellera and OSCI may help accelerate some existing standards efforts and foster new ones. "SystemC is getting more and more aligned with other design languages, so it makes perfectly good sense," he said. He noted that TLM 2.0 has become part of the Accellera Universal Verification Methodology (UVM), that some designers have expressed interest in UVM-SystemC and other languages, and that many designers would like to be able to move from SystemC to SystemVerilog in a more transparent manner.

Cadence Industry Insights
22 Jun 2011
OSCI announced plans to integrate with Accellera, comprehensive coverage of the new front-end design organization (Japanese)

The Accellera standards organization and ... Open SystemC Initiative ... announced plans to integrate the two organizations.

EDA Express
22 Jun 2011
Two design standards efforts combine forces

Accellera and the Open SystemC Initiative have signed a memorandum of understanding to form a single organization that will leverage the complementary EDA standards efforts of both groups.

EE Times
22 Jun 2011
Accellera and Open SystemC Initiative (OSCI) Get Engaged

System, software and semiconductor design activities are converging to meet the increasing challenges to create complex system-on-chips(SoCs). This convergence has brought to the forefront the need for a single organization to facilitate the creation of system-level standards and semiconductor design, and verification standards. The relationship between OSCI's TLM-2.0 SystemC Transaction Level Modeling standardand Accellera's Universal Verification Methodology (UVM) standard exemplifies the synergy that exists between the two organizations.

Gabe on EDA
22 Jun 2011
Accellera & OSCI Unite

In this evolution, it became clear to me that each organization was "completing" the other. OSCI has developed the popular Transaction Level Modeling (TLM) standards and Accellera had adopted TLM in their Universal Verification Methodology (UVM). As the technical teams from each organization have leveraged each other, it began to make more sense to initiate discussions to unite the two groups to address further front-end EDA standards challenges - as one. And, indeed, the two organization recognized this and have taken the steps to determine how best to combine operations into a single organization.

Mentor Verification Horizons Blog
21 Jun 2011
OSCI Welcomes Adoption of SystemC AMS 1.0 Standard Inside Industrial Design Flows for Mixed-Signal System Design

Recognized industry leaders NXP Semiconductors, STMicroelectronics and Infineon Technologies are integrating SystemC AMS extensions into their respective ESL design methodologies and mixed-signal design flows. The primary need is to enable the creation of mixed-signal virtual prototypes, where abstracted AMS models can be combined with the digital hardware/software subsystem for efficient and effective verification and validation of the entire system.

San Jose Mercury News
15 Mar 2011
Video: Eric Lish gives update on OSCI and SystemC

In a video interview blog, Open SystemC Initiative chair Eric Lish gives a quick update about SystemC and OSCI priorities going into 2011.

Cadence Industry Insights Blog
09 Mar 2011
TLM 2.0, UVM 1.0 and Functional Verification

The TLM2.0 standard was created for modeling memory-mapped buses in SystemC. Most of the DVCon discussion was devoted to the concepts of TLM 2.0, with a rich (or complex) set of capabilities. For example sockets and interfaces, blocking and non-blocking transports, the generic payload, hierarchical connection, temporal decoupling and more were covered. The main questions asked were: How much of this is relevant to functional verification and, specifically, UVM environments? What do I need to do differently in a UVM verification environment to leverage the TLM 2.0 potential?

Cadence Functional Verification Blog
07 Mar 2011
UVM Meets SystemC and VHDL in DVCon "Town Hall" Forum

Should the Universal Verification Methodology (UVM) work with SystemC? Should VHDL be extended with the object-oriented capabilities of SystemVerilog? Is it better to have interoperability between languages, or a unified language, or a language-neutral verification methodology? These questions and more were discussed and debated at a lively "town hall forum" lunch at the DVCon conference Feb. 28.

Cadence Industry Insights Blog
01 Mar 2011

<< Previous Results | Next Results >>

Past Media Coverage