Mantis 2399

P1800-2099/Draft 5

Corrections to Mantis 1619

In Section 22.2.24 (Default port values)

CHANGE

If an input port is left unconnected and the port does not have a default value, then, depending on the connection style (ordered list, name connections, implicit named connections, or implicit .* connections), the port shall either be left unconnected or result in an error, as discussed in 22.3.2.1 through 22.3.3.4.

TO

If an input port is left unconnected If a connection is not specified for an input port and the port does not have a default value, then, depending on the connection style (ordered list, named connections, implicit named connections, or implicit .* connections), the port shall either be left unconnected or result in an error, as discussed in 22.3.2.1 through 22.3.3.4.

In Section 22.3.2.1 (Connecting module instance ports by ordered list)

CHANGE

A blank port connection shall represent the situation where the port is not to be connected. If a port connection is omitted (indicated by a missing argument in the comma separated list) to an input port with a default value, the default value shall be used.

TO

A blank port connection shall represent the situation where the port is not to be connected. However, if If a port connection is omitted (indicated by a missing argument in the comma-separated list) to an input port with a default value, the default value shall be used.

CHANGE

module alu_accum1 (

output [15:0] dataout,

input [7:0] ain, bin,

input [2:0] opcode,

input clk, rst_n, rst);

wire [7:0] alu_out;

alu alu (alu_out, , ain, bin, opcode); // zero output is unconnected

accum accum (dataout[7:0], alu_out, clk, rst_n); // datain gets default

// value 8’hFF

xtend xtend (dataout[15:8], alu_out[7], clk); // rst gets default

// value 1'b0

endmodule

TO

module alu_accum1 (

output [15:0] dataout,

input [7:0] ain, bin,

input [2:0] opcode,

input clk, rst_n, rst);

wire [7:0] alu_out;

alu alu (alu_out, , ain, bin, opcode); // zero output is unconnected

accum accum (dataout[7:0], alu_out, clk, rst_n); // datain gets default

// value 8’hFF

xtend xtend (dataout[15:8], alu_out[7], clk); // rst gets default

// value 1'b0

endmodule

In Section 22.3.2.2 Connecting module instance ports by name

CHANGE

module alu_accum2 (

output [15:0] dataout,

input [7:0] ain, bin,

input [2:0] opcode,

input clk, rst_n, rst);

wire [7:0] alu_out;

alu alu (.alu_out(alu_out), .zero(),

.ain(ain), .bin(bin), .opcode(opcode));

// zero output is unconnected

accum accum (.dataout(dataout[7:0]), .datain(alu_out),

.clk(clk), .rst_n(rst_n));

// datain is not in the port list and so // gets default value 8’hFF

xtend xtend (.dout(dataout[15:8]), .din(alu_out[7]),

.clk(clk), .rst_n(rst_n));

// rst has a default value, but has an empty port connection,

// therefore it is left unconnected

endmodule

TO

module alu_accum2 (

output [15:0] dataout,

input [7:0] ain, bin,

input [2:0] opcode,

input clk, rst_n, rst);

wire [7:0] alu_out;

alu alu (.alu_out(alu_out), .zero(),

.ain(ain), .bin(bin), .opcode(opcode));

// zero output is unconnected

accum accum (.dataout(dataout[7:0]), .datain(alu_out),

.clk(clk), .rst_n(rst_n));

// datain is not in the port list and so // gets default value 8’hFF

// rst_n is not in the port list and so gets default value 1’b1

xtend xtend (.dout(dataout[15:8]), .din(alu_out[7]),

.clk(clk), .rst_n(rst_n) .rst());

// rst has a default value, but has an empty port connection,

// therefore it is left unconnected

In Section 22.3.2.3 Connecting module instance using implicit named port connections (.name)

CHANGE

To leave a port with a default value unconnected, open brackets must be used after .name, i.e. .name().

TO

To leave a port with a default value unconnected, open brackets empty parentheses must be used after .name, i.e. .name().

In Section 22.3.2.4 Connecting module instances using wildcard named port connections ( .*)

CHANGE

SystemVerilog can implicitly instantiate ports using a .* wildcard syntax for all ports where the instance port name matches the connecting port name and their data types are equivalent. This eliminates the requirement to list any port where the name and type of the connecting declaration match the name and equivalent type of the instance port. This implicit port connection style is used to indicate that all port names and types match the connections where emphasis is placed only on the exception ports. The implicit .* port connection syntax can greatly facilitate rapid block-level testbench generation where all of the testbench declarations are chosen to match the instantiated module port names and types.

An implicit .* port connection is semantically equivalent to a default .name port connection for every port declared in the instantiated module with two exceptions:

1) ...

2) Using .* does not create a sufficient reference for a wildcard import of a name from a package. A named port connection can be mixed with a .* connection to override a port connection to a different expression or to leave a port unconnected. A named or implicit .name connection can be mixed with a .* connection to create a sufficient reference for a wildcard import of a name from a package.

TO

SystemVerilog can implicitly instantiate ports using a .* wildcard syntax for all ports where the instance port name matches the connecting port name and their data types are equivalent. This eliminates the requirement to list any port where the name and type of the connecting declaration match the name and equivalent type of the instance port. This implicit port connection style is used to indicate that all port names and types match the connections where emphasis is placed only on the exception ports. A named port connection can be mixed with a .* connection to override a port connection to a different expression or to leave a port unconnected. The implicit .* port connection syntax can greatly facilitate rapid block-level testbench generation where all of the testbench declarations are chosen to match the instantiated module port names and types.

An implicit .* port connection is semantically equivalent to a default .name port connection for every port declared in the instantiated module with two exceptions:

1) ...

2) Using .* does not create a sufficient reference for a wildcard import of a name from a package. A named port connection can be mixed with a .* connection to override a port connection to a different expression or to leave a port unconnected. A named or implicit .name connection can be mixed with a .* connection to create a sufficient reference for a wildcard import of a name from a package.