Mantis 1984

P1800-2008/D4

22.2.2.3 says "For input and inout ports, if the port kind is omitted, then the port shall default to a net of net type wire." So, e.g., "input int" is illegal since nets can't be 2-state types or reals.

In 22.2.2.3, CHANGE

module mh1 (input int in1, input shortreal in2, output tagged_st out);

TO

module mh1 (input var int in1, input var shortreal in2, output tagged_st out);

CHANGE

module mh3 (input byte a, b);

TO

module mh3 (input var byte a, b);

In 22.10, CHANGE

interface range (input clk, enable, input int minval, expr);

TO

interface range (input clk, enable, input var int minval, expr);

ALSO:

The LRM has about 30 cases of "input bit" in module/program/interface declarations. The editor should change each of them to either "input var bit" or "input logic" or simply "input".

3.5: interface simple_bus(input bit clk); // Define the interface

6.20.1: interface simple_bus #(AWIDTH = 64, type T = word) // parameter port list

(input bit clk) ; // port list

14.12: program test( input bit clk, input reg [15:0] data );

16.14.4: module top(input bit clk); (NOTE: THIS LINE APPEARS TWICE!)

22.2.2.2:

module mymod (

output .P1(r[3:0]),

output .P2(r[7:4]),

ref .Y(x),

input bit R );

24.3.1:

module memMod( input bit req,

bit clk, (THIS LINE ALSO)

bit start, (THIS LINE ALSO)

...

module cpuMod(

input bit clk,

bit gnt, (THIS LINE ALSO)

bit rdy, (THIS LINE ALSO)

24.3.2:

module memMod(simple_bus a, // Access the simple_bus interface

input bit clk);

...

module cpuMod(simple_bus b, input bit clk);

...

module memMod (simple_bus sb_intf, input bit clk);

...

module cpuMod (simple_bus sb_intf, input bit clk);

24.3.3:

module memMod (interface a, input bit clk);

...

module cpuMod(interface b, input bit clk);

...

module memMod (interface a, input bit clk);

...

module cpuMod (interface b, input bit clk);

24.4: interface simple_bus (input bit clk); // Define the interface

24.5.1: interface simple_bus (input bit clk); // Define the interface

24.5.2: interface simple_bus (input bit clk); // Define the interface

24.5.3: interface simple_bus (input bit clk); // Define the interface

24.5.5: interface A_Bus( input bit clk );

24.7.1: interface simple_bus (input bit clk); // Define the interface

24.7.2: interface simple_bus (input bit clk); // Define the interface

24.7.3: interface simple_bus (input bit clk); // Define the interface

24.7.4: interface simple_bus (input bit clk); // Define the interface

24.8: interface simple_bus #(AWIDTH = 8, DWIDTH = 8)

(input bit clk); // Define the interface

24.9.1: interface SyncBus( input bit clk );

24.9.2: interface A_Bus( input bit clk );