Mantis 1489

Clarify top-level instances

P1800-2008/Draft 4

In Section 3.9,

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A design block that is elaborated but not instantiated becomes a top-level hierarchy block. SystemVerilog permits multiple top-level blocks.

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A design block module or program that is elaborated but not explicitly instantiated is implicitly instantiated once at the top of the hierarchy tree and becomes a top-level hierarchy block (see 22.3 and 23.3). SystemVerilog permits multiple top-level blocks.

In Section 22.3.1

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22.3.1 Top-level modules and $root

Top-level modules are modules that are included in the SystemVerilog source text, but do not appear in any

module instantiation statement, as described in 22.3.2. This applies even if the module instantiation appears in a generate block that is not itself instantiated (see 26.3). A design shall contain at least one top-level module.

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22.3.1 Top-level modules and $root

Top-level modules are modules that are included in the SystemVerilog source text, but do not appear in any

module instantiation statement, as described in 22.3.2. This applies even if the module instantiation appears in a generate block that is not itself instantiated (see 26.3). A design shall contain at least one top-level module.

A top-level module is implicitly instantiated once, and its instance name is the same as the module name. Such an instance is called a top-level instance.