Section Table 3-1, 3.6, 3.9, 3.11, 7.6, 7.8, 7.17, 8.4, 8.4.1.1, 8.5.3, Syntax 10-1, 10.3.1, 19.4, A.5.2, A.10.25
Design clarifications and typos

In 19.4, before the paragraph beginning “In a hierarchically nested interface”, INSERT

If a port connection specifies a modport list name in both the module instance and module header declaration, then the two modport list names shall be identical.

In 8.4, in the example, REPLACE

run-time error

WITH

run-time warning

In 8.4, at the end of the section, REPLACE

priority casez(a)

2’b00?: $display(“0 or 1”);

2’b0??: $display(“2 or 3”);

default: $display(“4 to 7”);

endcase

The unique and priority keywords shall determine the simulation behavior. It is recommended that synthesis follow simulation behavior where possible. Attributes can also be used to determine synthesis behavior.

WITH

priority casez(a) // values 4,5,6,7 cause a run-time warning

3’b00?: $display(“0 or 1”);

3’b0??: $display(“2 or 3”);

endcase

The unique and priority keywords shall determine the simulation behavior. It is recommended that synthesis follow simulation behavior where possible. Attributes can also be used to determine synthesis behavior.

BUT using “ instead of “” (which is an artifact of my editor).

In 8.5.5, add tabs to the bodies of the first two examples of the foreach construct.

On pages 26, 73, and 86, REPLACE

bit [1:0] cc,

WITH

bit [1:0] cc;

In Table 3-1, REPLACE

64-bit integer

WITH

64-bit unsigned integer

In 3.6, remove the trailing period (.) after

successive runs of the same tool

In 3.9, REPLACE

intf_i_i

WITH

intf_i

In 3.11, in the first example, remove one tab stop from the line beginning

IR.opcode = 1 ;

In 7.6, REPLACE

If any operand is real, the result is real, except before the ? in the ternary operator. If no operand is real and any operand is shortreal, the result is shortreal.

WITH

If any operand, except before the ? in the ternary operator, is real, the result is real. Otherwise, if any operand, except before the ? in the ternary operator, is shortreal, the result is shortreal.

In 7.8, REPLACE

The following unary operators give the signedness of the operand: ~ ++ -- + -. All other operators shall follow the same rules as Verilog for performing signed and unsigned operations.

WITH

The rules for determing the signedness of SystemVerilog expression types shall be the same as those for Verilog. A shortreal converted to an integer by type coercion shall be signed.

Throughout 7.17, float should not be bold.

In 8.5.3, in the last example, the keyword bit should be bold.

In 10.3.1, fix the formatting of the comment in the second example.

In Footnote 25 of A.10, REPLACE

additional packed dimensions are not permitted

WITH

an additional packed dimension is not permitted