================================================================ Addendum to Review of Section 3 of SystemVerilog LRM Draft 4 Rishiyur S. Nikhil Feb 10, 2004 ---------------------------------------------------------------- Section '3.14 Casting' In 2nd sentence, "The expression to be cast must be enclosed in parenthesis ..." Typo: "... parenthesis ..." Should be "... parentheses ..." ---------------------------------------------------------------- Section '3.14 Casting' 2nd sentence "The expression to be cast must be enclosed in parenthesis or within concatenation or replication braces and is self-determined." Problem (see email by Greg Jaxon): Contatenation and replication braces are often not self-determined, see text and examples in Section 2.7, 2.8, 7.14. Suggested replacement for the sentence: "The expression to be cast is self-determined if it is enclosed in parentheses, or if it is enclosed in contatenation or replication braces and is being cast to a singular type. If it is enclosed in contatenation or replication braces and is cast to an aggregate type, then that aggregate type forms an assignment context for the expression." ================================================================