Section 26.4.4

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Editor’s Note: Is the preceding cross reference correct?

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// Note the following import uses the same foreign function for

// implementation as the prior import, but has different SystemVerilog name

// and provides a default value for the argument.

import "DPI" newQueue=function handle newAnonQueue(input string s=null NULL);

Remove editor’s note:

Editor’s Note: Is the uppercase “NULL” correct? The SystemVerilog keyword is in lowercase.

Section 26.4.6.1

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logic

bit [8:1]

bit[]

bit [7:0] array8x10 b8x10 [1:10] // array8x10 b8x10 is a formal arg name

logic [31:0] array32xN l32x [] // array32xN l32x is a formal arg name

logic [] arrayNx3 lx3 [3:1] // arrayNx3 lx3 is a formal arg name

bit [] arrayNxN an_unsized_array [] // arrayNxN an_unsized_array is a formal arg name

Remove editor’s note:

Editor’s Note: It is illegal in Verilog to start a name with a number (e.g. “132x”. Does that rule apply here?