Section 3.4

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Delete the entire section 3.4

 

3.4 Time data types

 

Time is a special data type. It is a 64 bit integer of time steps. The default time step follows the rules of IEEE Verilog standard. The time step can be changed by the timeprecision declaration. It can also be changed by a ‘timescale directive.

 

The timeprecision declaration affects the local accuracy of delays.

 

module m;

timeprecision 0.1ns;

initial #10.11ns a = 1; // round to #10.1ns according to time precision

endmodule

 

The timeunit declaration is used to set the current time unit. When a literal time is expressed in SystemVerilog, it can be given with explicit time units, e.g. 12ns. If no time units are specified, the literal number is multiplied by the current time unit. Time values are scaled to the time precision of the module, following the rules of Verilog-2001. An integer or real variable is cast to a time value by using the integer or real as a delay.

 

For example:

 

#10.11; // multiply by time unit and round according to time precision

 

See Section 18.6 for more information on setting the time units and time precision.

Remove Editor’s Note:

Editor’s Note: BC08-05 says to “Remove section 3.4.1”. There is no such section, and the change order does not have the requisite details of which version it referred to, or what text is to be deleted.

Section 3.7

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The use of chandles is are restricted as follows:

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— In structures or unions

— In packed type arrays

Section 3.8

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In SystemVerilog string literals behave exactly the same as in Verilog. However, SystemVerilog also supports the string data type to which a string literal can be assigned. When using the string data type instead of a packed array, strings can be of arbitrary length and no truncation occurs. Literal strings are implicitly converted to the string type when assigned to a string type or used in an expression involving string type operands.

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SystemVerilog provides a set of operators that can be used to manipulate combinations of string variables and string literals. The basic operators defined on the string data type are listed in Table 3-2, which follows.

 

A string literal is implicitly converted to string type when it is assigned to a variable of type string or is used in an expression involving string type operands. A variable of type string can be assigned an expression of type string, string literal, or packed array.

 

A string literal can be assigned to a string, a character, or a packed array. If their size differs the literal is right justified and zero filled on the left. For example:

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Changes (semantics section for Concatenation of Table 3-2):

Concatenation. Each string operand may be of type string or a string literal (it will be implicitly converted to type string). If at least one string operand is of type string, then the expression evaluates to the concatenated string and is of type string. If all the strings operands are string literals then the expression behaves like a Verilog concatenation of integral types; if the result is then used in an expression involving string types, it is implicitly converted to the string type.

Section 3.8.9

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Editor’s Note: “integer” or “int”?

Section 3.10

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A typedef inside a generate may shall not define the actual type of a forward definition that exists outside the scope of the forward definition.

Remove Editor’s Note:

Editor’s Note: Does “may not” in the preceding paragraph indicate a mandatory rule or an optional rule? If mandatory, then change to “shall”. If optional, the sentence needs to be rephrased to not be ambiguous.

Section 3.11

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An unassigned enumerated name that follows and enum name with x or z assignments shall be a syntax error.

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Adding a constant range to the enum declaration can be used to set the size of the type. If any of the enum members are defined with a different sized constant, this shall be a syntax error.

 

// Error in the bronze and gold member declarations

enum bit [3:0] {bronze=5’h13, silver, gold=3’h5} medal4;

 

// Correct declaration - bronze and gold sizes are redundant

enum bit [3:0] {bronze=4’h13, silver, gold=4’h5} medal4;

 

Type checking of enumerated types used in assignments, as arguments and with operators is covered in Section 3.11.3. Like C, there is no overloading of literals, so medal and medal4 cannot be defined in the same scope, since they contain the same names.

Section 3.11.3

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SystemVerilog enumerated types are strongly typed, thus, a variable of type enum cannot be directly assigned a value that lies outside the enumeration set. This is a powerful type-checking aid that prevents users from accidentally assigning nonexistent values to variables of an enumerate type. This restriction only applies to an enumeration that is explicitly declared as a type. The enumeration values can still be used as constants in expressions, and the results can be assigned to any variable of a compatible integral type.

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Casting can be used to perform an assignment of a different data type, or an out of range value, to an enumerated type. Casting is discussed in Sections 3.11.4, 3.14 and 3.15.

Section 3.11.4

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From the previous declaration, blue has the numerical value 2. This example assigns a the value of 6 (2*3). Next, it assigns b a value of 4 (3+1).

 

Methods for iterating over enumerated types

 

SystemVerilog includes a set of specialized methods to enable iterating over the values of enumerated types.

 

An enum variable or identifier used as part of an expression is automatically cast to the base type of the enum declaration (either explicitly or using int as the default). An assignment to an enum variable from an expression other than an enum variable or identifier of the same type shall require a cast. Casting to an enum type shall cause a conversion of the expression to its base type without checking the validity of it the value (unless a dynamic cast is used as described in Section 3.15).

 

typedef enum {Red, Green, Blue} Colors;

typedef enum {Mo,Tu,We,Th,Fr,Sa,Su} Week;

Colors C;

Week W;

int I;

 

C = Colors’(C+1);                 // C is converted to an integer, then added to

// one, then converted back to a Colors type

 

C = C + 1; C++; C+=2; C = I;      // Illegal because they would all be

// assignments of expressions without a cast

 

C = Colors’(Su);                  // Legal; puts an out of range value into C

 

I = C + W;                        // Legal; C and W are automatically cast to int

 

SystemVerilog includes a set of specialized methods to enable iterating over the values of enumerated types.

Section 3.11.4.2

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The last() method function returns the value of the last member of the enumeration enum.

Section 3.11.4.3

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The next() member function returns the Nth next enumeration value (default is the next one) starting from the current value of the given variable. A wrap to the start of the enumeration occurs when the end of the enumeration is reached. If the given value is not a member of the enumeration, the next() member function returns the first member.

Section 3.11.4.4

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The prev() member function returns the Nth previous enumeration value (default is the previous one) starting from the current value of the given variable. A wrap to the end of the enumeration occurs when the start of the enumeration is reached. If the given value is not a member of the enumeration, the prev() member function returns the last member.

Section 3.11.4.6

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The name() method returns the string representation of the given enumeration value. If the given value is not a member of the enumeration, the name() member function returns the empty string.

Section 3.12

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If any data type within a packed structure is 2 4-state, the whole structure is treated as 2 4-state. Any  4  2-state members are converted as if cast, i.e. an X will be read as 0 if it is in a member of type bit. One or more elements of the packed array may be selected, assuming an [n-1:0] numbering:

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A packed union shall contain members that must be packed structures, or packed arrays or integer data types all of the same size (in contrast to a union where the members can be different sizes). This ensures that you can read back a union member that was written as another member. A packed union can also be used as a whole with arithmetic and logical operators, and its behavior is determined by the signed or unsigned keyword, the latter being the default. If a packed union contains a 2-state member and a 4-state member, the entire union is 4 state. There is an implicit conversion from 4-state to 2-state when reading and from 2-state to 4-state when writing the 2-state bit member.