Section 18.5

LRM-200

Changes:

module mh4(x, y);

wire int x;

tri0 byte y;

...

endmodule

Changes:

A software tool can use the port direction to check against writing to an input port or not writing to an output port.

 

Ports which are of a net type can have multiple drivers, which are resolved according to the net’s resolution function. A driver can be an output port of an instantiation, or a continuous assignment.

 

If the port is of type logic or any other variable data type, then the port has the value of the last assignment to it. If the port is an inout, then these assignments can be inside or outside the module. If the port is an output, then these assignments shall only be inside the module. This provides a way to model a port which is meant to be a single driver.

Section 18.6

LRM-249

Changes:

There can shall be only one time unit and one time precision for any module or interface definition, or in $root. This shall define a time scope. If specified, the timeunit and timeprecision declarations shall precede any other items in the current time scope. The timeunit and timeprecision declarations can be repeated as later items, but must match the previous declaration within the current time scope.

Section 18.7

LRM-2

Remove editor’s note:

Editor’s Note: “parameter” is a Verilog keyword, and “parameterized” models refer to the usage of Verilog “parameters” (see Sections 11.21, 19.6 and 20). Use of the word “parameterized” in this context is not consistent with the Verilog LRM. Suggest using “arguments” (as in Verilog LRM), “formal arguments” or “formals”.

Section 18.7.3

LRM-25

Changes:

A .name .port_identifier port connection is semantically equivalent to the named port connection .port_identifier(name) .name(name) port connection with the following exceptions:

 

The identifier referenced by .name .port_identifier shall not create an implicit wire declaration.

— It shall be illegal for a .name .port_identifier port connection to create an implicit cast. This includes truncation or padding.

— A conversion between a 2-state and 4-state type of the same bit length is a legitimate cast.

— A port connection between a net type and a variable type of the same bit length is a legitimate cast.

— It shall be an error if a .name .port_identifier port connection between two dissimilar net types would generate a warning message as required by the Verilog-2001 standard.

Section 18.8.3

LRM-26

Changes:

See Section XX for more port connection rules with interfaces.

Remove editor’s note:

Editor’s Note: What is the cross reference for above?