Note 1: Should give some motivations here as to how/why assertions are useful.
CHANGE: First paragraph reworded:
SystemVerilog adds features to specify assertions of a system. An assertion specifies a specific behavior of the system. Assertions are primarily used to validate the behavior of a design. In addition, assertions can be used to provide functional coverage and generate input stimulus for validation. 

Note 2:semantic, not semantics
CHANGE: Fixed

Note3: I would move this sentence into the fail section of this paragraph. 

Also I would rather see the text in ()'s reworded without the ()'s so that they appear as regular sentences (this is me being picky). ;^)

RESPONSE: It describes the semantic of true/false at the same time.

CHANGE: () removed.

Note 3: For this whole section I understand that:

A pass statement is optional and if omitted then nothing will happen if an asseriton is passing.

And a fail statement is also optional - if omitted then an error is thrown, but if not omitted then ONLY the user-specific action will be taken, not both.

I read this later in the document, but I would like to see it more clearly stated here.

RESPONSE: The default action is described along with the severity.

Note 4: "words" should be "phrases"
RESPONSE: THis note has been deleted. Only clock tick is used in the document.

Note5: This paragraph should have a "why/what are sequences for".
CHANGE: Asentence added "Properties are often constructed out of sequential behavior. The sequence feature provides the capability to build and manipulate sequential behavior."

Note 6: in a non-negative integer

then the second bullet below can be deleted...
RESPONSE: Just for clarity, two bullets are used

Note 7: s/b ##2, not ##22
RESPONSE: Fixed

Note 8: How about "Expression concatenation"?
RESPONSE: Changed to concatenation of sequences

Note 8: How about this sentence?

The $ symbol can be used to represent time at the end of the simulation, as in the example below.

CHANGE: Sentence rephrased: "The $ symbol is used to represent time at the end of the simulation, as in the example below"

Note 9:
Maybe replace end of this sentence with:

of an expression, its name can be simply referenced.
RESPONSE: The sentence fixed as: "To use sequence as a sub-expression, or a part of the expression, its name is simply referenced"

Note 10:
illustrates an illegal dependency...
CHANGE: fixed

Note 11:
replace "which" with "because it"
CHANGE: Fixed

Note 12: Should the "should"s in this paragraph be replaced with "must"s?
CHANGE: Fixed

Note 13: forgot the usual "//" comment indicators
RESPONSE: "means" is used to be more explicit.

Note 14: "in turn" instead of second "which"
CHANGE: Fixed

Note 15: How about changing this example to have ##2 instead of ##1, so that the expanded example after it can become clearer?
CHANGE: Fixed

Note 16: Same comment here for the ##1 to be ##2
CHANGE: Fixed

Note 17: need an "a" here
CHANGE: Fixed

Note 18: add: (i.e. not the only term in the expression)
CHANGE: Fixed

Note 19: I didn't see any explicit mention of X and Z behavior.  I guess this implication is clear enough to the user?
RESPONSE: The description is similar to posedge and negedge

Note 20: Do we need a "must" before the word "start"?
RESPONSE: No. because that always happens.

Note 21: replace "of" with "for a"
CHANGE: Fixed

Note 22: add "an" after "attempt"
CHANGE: Fixed

Note 23: replace "end" with "start and end"?
RESPONSE: No, because start times are always the same

Note 24: Here and later in the chapter I see the words "match" and "succeed" used interchangably.  I would rather see just one word used, unless there is some difference I didn't understand.
RESPONSe: No they mean the same.  Success is generally used for a property, while a match is used for a sequence.

Note 25: should this be:

first_match(t2);
CHANGE: Fixed

Note 26: Should delete either "Also" or "frequently".
CHANGE: Fixed

Note 27: For this "ended" and the later "matched" method, why not use syntax like the first_match operator?
RESPONSE: ASWG committee decided to use a method, to reduce the keywords. ALso, ended happens on sequences, so it seemed appropriate.

Note 26: I know it's *way* too late for this, but I would rather have |=> be the overlap operator because the "=" helps convey the shared start/end time.
RESPONSe: This was decided to align with the PSL syntax.

Note 27: Here the "property" keyword is used without an introduction.
RESPONSE: In Verilog manual it is the style. Not everything is introduced before usage. In this case, it is not important to understand property construct. But, since implication can only appear in a property, it became unavoidable.

Note 28: should this be "end_data1" ?
RESPONSE: This has been changed to data_end_exp

Note 28: since this is essentially a continued sentence, should the "S" be lowercase?
RESPONSe: Already fixed.

Note 29: It's a little tricky here to talk about verification and assertion because these haven't been fully discussed until the end of the section.
CHANGE: The word assertion removed.

Note 30: Need to better explain "copy" here.
CHANGE: The sentence rephrased as "The use of static SystemVerilog variables implies that only one copy exists."

Note 31: should be "copy" instead of "instance" to be consistent.
CHANGE: Fixed

Note 32: should also include "throughout" ???
RESPONSE: No. In throughout, there is no assignment for the boolean expression. There are no parallel branches like in and, or and intersect.

Note 33: more clearer to see:

"is not sampled in either branch"
CHANGE: Fixed

Note 34: more clearer to see:

"is not sampled in either branch"
RESPONSE: The description has changed to:
In the case of and and intersect, the symmetric difference of the local variables that are sampled in the two joining threads passes on past the join. More precisely, a local variable that passes through at least one branch of the join will be passed on past the join unless it is blocked. A local variable is blocked from passing on past the join if either:

Note 35: "is" should be "can be"
RESPONSE: The sentence now reads: "A property is declared with optional formal arguments,"

Note 36: "disabble" should be "disable"
RESPONSE: Typo already fixed

Note 37: change:

clk to clk0
a to sig0
b to sig1

and this will be easier to read and not require the second example
CHANGE: Fixed

Note 38: in the rest of these bullet headings (2-6) change "clocked" to "clock"
CHANGE: Fixed

Note: see syntax question for "ended"
RESONSE: Same response


Note 39: Rather see 1st sentence as something like:

A property on its own is never evaluated for checking an expression.  It must be used within a verification statement for this to occur.

CHANGE: Fixed

Note 40: should be: "assert or cover statement"
CHANGE: Fixed

Note 41: what is an attemptID? - this was never defined
CHANGE: Sentence changed to "Each attempt with an identifier (attemptID) and time"

Note 42: statement. not statements
CHANGE: Fixed

Note 43: need "an" here
CHANGE: Fixed

Note 44: strike "the"
CHANGE: Fixed

Note 45: missing introduction / syntax definition of "default" and "clocking" before use
RESPONSE: This construct is defined in clocking domain

Note 46: Need to define "identical" here and for the following tables.  Can it mean two clocks with timing behavior or literally the same signal instance?
RESPONSE: The definition of identical is left to the tools. If the tools can analyze may determine that the clocking expressions are equivalent, or a user may direct a tool to make two clocks identical. In the worst case, the two clocks are syntactically equivalent.

Note 46: missing "a"
Note 47: s/b "statements"
Note 48: replace comma with "or"
Note 49: I agree with the editor here (and of course everywhere else. ;^)
RESPONSE: Template feature is dropped for SV3.1

Note 50: For these examples, please add more Verilog source to the fragments to better show the differences between binding modules vs. instances.
CHANGE: Bind is extended to interface also. A full example is provided.