Extern Module Proposal

Issue:  .* cannot be implemented in a separate compilation scenario like
	DC uses because the downside ports cannot be known.

	The issue is more complicated by the fact that if the downside
	contains a generic interface, the upside is needed to know the 
	type of the downside port.

Solution:  The idea for this proposal is to allow extern declarations of
	modules. An extern module declaration of module x will include 
	the ports of the module.  The module x can have .* as its 
	portlist, which will result in the use of the ports from the 
	extern declaration.

Standar changes in Section 12.7.4 Instantiation using implicit .* port connections

	At the end of 12.7.4 ADD:

	To support separate compilation, extern declarations of a 
	module can be used to declare the ports on a module without 
	defining the module itself.  An extern module declaration 
	consists of the keyword extern followed by the module name, 
	and the list of ports for the module.  Both list of ports 
	syntax (possibly with parameters), and original Verilog 
	style port declarations may be used.  Note that the potential
	existence of defparams precludes the checking of the 
	port connection information prior to elaboration time even for
	list of ports style declarations.

	The following example demonstrates the usage of extern 
	module declarations.

	extern module m (a,b,c,d);
        extern module a #(parameter size= 8, parameter type TP = logic[7:0]) 
                       (input [size:0] a, output TP b);

	module top ();
	    wire [8:0] a;
	    logic [7:0] b;

	    m m (.*);
	    a a (.*);
	endmodule

	Modules m and a are then assumed to be instantiated as:

	module top ();
	    m m (a,b,c,d);
	    a a (a,b);
	endmodule

	If an extern declaration exists for a module, it is possible to
	use .* as the ports of the module.   This usage will be equivalent
	to placing the ports (and possibly parameters) of the extern 
	declaration on the module.  For example,

	extern module m (a,b,c,d);
        extern module a #(parameter size= 8, parameter type TP = logic[7:0]) 
                       (input [size:0] a, output TP b);
	
	module m (.*);
	    input a,b,c;
	    output d;
	endmodule

	module a (.*);
	endmodule

	is equivalent to writing:

	module m (a,b,c,d);
	    input a,b,c;
	    output d;
	endmodule

	module a #(parameter size= 8, parameter type TP = logic[7:0]) 
                       (input [size:0] a, output TP b);
	endmodule

	Extern module declarations can appear at any level of the 
	instantiation hierarchy, but are visible only within the level of 
	hierarchy in which they are declared.  It shall be an error for 
	the module definition to not exactly match the extern module 
	declaration.