Passed 7/22/02:

In Section 3.7 page 11

Update the paragraph as indicated in red:

A packed union shall contain members that are packed structures, or packed arrays or integer data types of the same size. This ensures that you can read back a union member that was written as another member. If any member is 4-state, the whole union is 4-state. A packed union can also be used as a whole with arithmetic and logical operators, and its behavior is determined by the signed or unsigned keyword, the latter being the default.

In Section 2.3

Add to the last paragraph of section 2.3 the sentence:

In a self-determined context these literals have a width of 1 bit.

In Section 2.7

Update the sentence as indicated in red:

Array literals are syntactically similar to C initializers, but with the replicate operator ( {{}} ) allowed.

In Section 2.8

Update the sentence as indicated in red:

Structure literals are syntactically similar to C initializers. Structure literals must have a type, either from context or a cast.

Passed 8/19/02:

In Section 2.3:

Update the sentence as indicated in red:

SystemVerilog adds the ability to specify unsized literal single bit values with a preceding apostrophe ( ‘ ), but without the base specifier. All bits of the unsized value are set to the value of the specified bit, and the value is treated as unsigned.

In Section 3.7:

Update the sentence as indicated in red:

Like a packed array, a packed structure can be used as a whole with arithmetic and logical operators. The first member specified is the most significant and subsequent members follow in decreasing significance. The structures are declared using the packed keyword, which can be followed by the signed or unsigned keywords, according to the desired arithmetic behavior, which defaults to unsigned:

In Section 3.7:

REPLACE:

"A packed union contains members that are packed structures or arrays of the same size."

WITH:

"A packed union contains members that must be packed structures or arrays of the same size."

 

In Section 3.6:

After the "A sized constant" paragraph and example place:

// Syntax error: the width of the enum has been exceeded in both of these examples

enum {a=1'b0, b, c} alphabet;

enum [0:0] {a,b,c} alphabet;

Any enumeration encoding value that is outside the representable range of the enum shall be an error.

In Section 3.6:

REPLACE:

An enumerated name with x or z assignments assigned to an enum with no explicit data type

declaration shall be a syntax error.

WITH:

An enumerated name with x or z assignments assigned to an enum with no explicit data type

or an explicit 2-state declaration shall be a syntax error.

In Section 3.6:

After the first paragraph add:

The format control string "%n" can be used to display the enumerated name. Any format control string which can be used to display an integer value can be used to display an enumerated value.

In Table 7.2:

add ^~ to table 7.2 on the 2nd line of the table and on the 11th.

In A.1.1:

Update as indicated in red:

library_declaration ::=

library library_identifier file_path_spec [ { , file_path_spec } ]

[ -incdir file_path_spec [ { , file_path_spec } ] ] ;

In A.1.2:

Update as indicated in red:

liblist_clause ::= liblist [{library_identifier}]

In A.1.4:

Update as indicated in red:

port_expression ::=

port_reference

| { port_reference { , port_reference } }

The outer braces ( {} ) should be in bold in order to enable concatenated ports (same as the IEEE 1364-2001 standard)

 

 

 

In A.1.6:

Update as indicated in red:

interface_or_generate_item ::=

{ attribute_instance } continuous_assign

| { attribute_instance } initial_construct

| { attribute_instance } always_construct

| { attribute_instance } combinational_statement

| { attribute_instance } latch_statement

| { attribute_instance } ff_statement

| { attribute_instance } local_parameter_declaration

| { attribute_instance } parameter_declaration ;

| module_common_item

| { attribute_instance } modport_declaration

interface_item ::=

port_declaration ;

| non_port_interface_item

A semi-colon (;) is missing after the port declaration

In A.1.6:

Delete lines as indicated in red:

non_port_interface_item ::=

{ attribute_instance } generated_interface_instantiation

| { attribute_instance } local_parameter_declaration

| { attribute_instance } parameter_declaration ;

| { attribute_instance } specparam_declaration

| interface_or_generate_item

| interface_declaration

The syntactic categories "parameter_declaration" and "local_parameter_declaration" can be parsed by parsing the "interface_or_generate_item" syntactic category

In A.2.1.2:

interface_port_declaration ::=

interface list_of_interface_identifiers

| interface . modport_identifier list_of_interface_identifiers

| identifier list_of_interface_identifiers

| identifier . modport_identifier list_of_interface_identifiers

The token identifier is not a keyword therefore it should not be printed in bold text

In A.2.1.3:

Bold brackets as indicated in red:

type_declaration ::=

typedef data_type type_declaration_identifier ;

| typedef interface_identifier { [ constant_expression ] } . type_identifier

type_declaration_identifier ;

 

 

 

 

In A.2.2.1:

Update as indicated in red:

signing ::= [ signed ] | [ unsigned ]

The square brackets are not needed due to the fact that every rule that parses the "signing" token already encloses the token with square brackets.

In Section A.2.3:

Update as indicated in red:

list_of_event_identifiers ::= event_identifier [ unpacked_dimension { unpacked_dimension }]

{ , event_identifier [ unpacked_dimension { unpacked_dimension }] }

The suggested rule is equivalent to the original rule but is simpler.

In Section A.2.3:

Update as indicated in red:

list_of_net_identifiers ::= net_identifier [ unpacked_dimension { unpacked_dimension }]

{ , net_identifier [ unpacked_dimension { unpacked_dimension }] }

The suggested rule is equivalent to the original rule but is simpler.

In Section A.1.3:

Update as indicated in red:

module_declaration ::=

{ attribute_instance } module_keyword module_identifier [ parameter_port_list ]

[ list_of_ports ] ; [ timeunits_declaration ] { module_item }

endmodule

| { attribute_instance } module_keyword module_identifier [ parameter_port_list ]

[ list_of_port_declarations ] ; [ timeunits_declaration ] { non_port_module_item }

endmodule

In case of a module declaration that isn’t followed by neither a port list nor a port declaration list then the module declaration should be parsed using the second rule.

module_keyword ::= module | macromodule

interface_declaration ::=

{ attribute_instance } interface interface_identifier [ parameter_port_list ]

[ list_of_ports ] ; [ timeunits_declaration ] { interface_item }

endinterface [: interface_identifier]

| { attribute_instance } interface interface_identifier [ parameter_port_list ]

[ list_of_port_declarations ] ; [ timeunits_declaration ] { non_port_interface_item }

endinterface [: interface_identifier]

In case of a interface declaration that isn’t followed by neither a port list nor a port declaration list then the interface declaration should be parsed using the second rule.

 

 

 

 

 

 

 

In Section A.2.2.3

REPLACE: delay3, delay2, and delay_value productions

WITH:

delay3 ::= # delay_value | #( mintypmax_expression [,

mintypmax_expression [, mintypmax_expression]])

delay2 ::= # delay_value | #( mintypmax_expression [,

mintypmax_expression])

delay_value ::= unsigned_number

| real_number

| identifier

In Section 3.7:

REPLACE:

This ensures that you can read

back a union member that was written as another member. If any member is

4-state, the whole union is 4-state. A

packed union can also be used as a whole with arithmetic and logical

operators, and its behavior is determined by the

signed or unsigned keyword, the latter being the default.

WITH:

This ensures that you can read back a union member that

was written as another member. A packed union can also be used as a

whole with arithmetic and logical operators, and its behavior is

determined by the signed or unsigned keyword, the latter being the

default. If a packed union contains a 2-state member and a 4-state

member, the entire union is 4 state. There is an implicit conversion

from 4-state to 2-state when reading and from 2-state to 4-state when

writing the 2-state bit member.

In A.2.2.1:

Update as indicated in red:

port_type ::=

data_type { packed_dimension }

| net_type [ signing ] { packed_dimension }

| trireg [ signing ] { packed_dimension }

| event

| [ signing ] { packed_dimension } range

The port_type syntactic category already parses the packed dimensions if needed how ever the optional packed dimension addition in this rule will enable illegal port declarations such as: "output integer [10:0] a;"

 

 

 

 

 

 

 

 

 

In A.2.7:

Update as indicated in red:

task_item_declaration ::=

block_item_declaration

| { attribute_instance } input_declaration ;

| { attribute_instance } output_declaration ;

| { attribute_instance } inout_declaration ;

task_port_list ::= task_port_item { , task_port_item }

list_of_port_identifiers { , task_port_item }

task_port_item ::=

{ attribute_instance } input_declaration

| { attribute_instance } output_declaration

| { attribute_instance } inout_declaration

| { attribute_instance } port_type list_of_port_identifiers

This change is needed to support default port types as described in page 38 of the System-Verilog LRM. This will enable the parsing of task declarations such as :

"task mytask3(a, b, output logic [15:0] u, v);"

and

"task mytask3(logic a, b, output logic [15:0] u, v);"

In Section 10.2:

Page 38 in SV3.0 LRM, second paragraph.

OLD Language:

The default type in SystemVerilog is logic,

which is compatible with Verilog.

NEW Language:

The task argument default type in SystemVerilog is reg.

In A.2.9:

Update as indicated in red:

modport_port ::=

input [port_type] port_identifier

| output [port_type] port_identifier

| inout [port_type] port_identifier

| interface_identifier . port_identifier

| import_export task named_task_proto

| import_export function named_function_proto

| import_export task_or_function_identifier { , task_or_function_identifier }

Fixing a typo the syntactic category is named "named_function_proto".

In A.4.1.1:

Update as indicated in red:

named_parameter_assignment ::=

. parameter_identifier ( [ expression ] )

| . parameter_identifier ( [ data_type ] )

An empty parameter assignment can be parsed using both rules

 

In A.4.2.1:

genvar_assignment ::=

genvar_identifier = constant_expression

| genvar_identifier assignment_operator constant_expression

| inc_or_dec_operator genvar_identifier

| genvar_identifier inc_or_dec_operator

The rule ’genvar_assignment ::= genvar_identifier = constant_expression’ is redundant to the rule ‘genvar_assignment ::= genvar_identifier assignment_operator constant_expression’ due to the fact that the assignment operator includes the equal sign (=).

In A.6.4:

Update as indicated in red:

statement_item ::=

……

| { attribute_instance } inc_or_dec_expression ;

A semi-colon (;) is needed here

……

| { attribute_instance } inc_or_dec_expression ;

A semi-colon (;) is needed here