I would suggest that the implicit ".name" and  ".*" port
connection syntax in sections 12.7.3-4 of the System Verilog 3
standard be extended to allow partial name matching of ports
when implying the connection to variables.  

For example 
   alu alu1 ( .alu_out(alu_out1), .*in(*in1),    .* );
   alu alu2 ( .alu_out(alu_out2), .*in(*in2),    .* ); 
   
This would imply the .ain(ain1) and .bin(bin1) connections
for alu1 and the .ain(ain2) and .bin(bin2) connections for alu2.

We have an internal tool that converts this syntax to verilog95
and we have found this syntax of abbreviation extremely intuitive
and useful. 

When multiple patterns match a named pin, pattern listed first
in the port list shall be expanded. This might imply that ".name"
and ".*" could be used together in a port list, as long as the
".name" connection preceded the ".*" connection.