Minutes of the 10/14/02 SV-BC Meeting. This is my list of attendees and voting status - please submit corrections: (aa-aaaaa) Cliff Cummings (Sunburst Design) * (aaaaaaaa) David Smith (Synopsys) * (---aa--a) Heath Chambers (HMC) (aaaaaaaa) Karen Pieper (Synopsys) * (aaaaaa-a) Kevin Cameron (NSC) * (---aa---) Medi Mohtashemi (Synopsys) (---aa---) Paul Graham (Cadence) (---aaaaa) Peter Flake (Co-Design) * (---aaaa-) Simon Davidmann (Co-Design) * (--aaaaaa) Stefen Boyd (Boyd Technology) * (aaaaaa-a) Steven Sharp (Cadence) * (----aaa-) Dave Kelf (Co-Design) * (aaa-aaa-) Dennis Brophy (Model Technology) * (aa--aa--) Mike McNamara (Verisity) (a---aaaa) Tom Fitzpatrick (Co-Design) * (-----aaa) Vasisilios Gerousis (Seimens) * (-a----aa) Francoise Martinolle (Cadence) (-------a) Don Mills (LCDM Engineering) (aaa----a) Gord Vreugdenhil (Synopsys) (aaa-----) Brad Pierce (Synopsys) * indicates eligible to vote on consensus issues Minutes from the 9/30 Meeting (can be found at http://www.eda.org/sv-bc). Dennis moves that we approve the minutes. Gord seconds. No opposed. No abstains. Passes. Action Items: Karen has organized a meeting for 11/15 for SV-BC face to face. We will discuss interfaces and any other issues where we need to ask for information on Co-Design's implementation. Karen's proposed insertion of SV-BC17b,c. Karen moves that we approve those changes. Steven seconds. For SV-BC17d: After the "A sized constant" paragraph and example place // Syntax error: the width of the enum has been exceeded in both of these examples enum {a=1'b0, b, c} alphabet; enum [0:0] {a,b,c} alphabet; Any enumeration encoding value that is outside the representable range of the enum shall be an error. Cliff proposes this. Gord seconds. No opposed. No abstain. Passes. For SV-BC17b: REPLACE: An enumerated name with x or z assignments assigned to an enum with no explicit data type declaration shall be a syntax error. WITH: An enumerated name with x or z assignments assigned to an enum with no explicit data type or an explicit 2-state declaration shall be a syntax error. Karen proposes. Cliff seconds. No opposed. No abstain. Passes. Steven needs to drive the creation of the document with the arguments for deleting the "static" keyword. He will work with Gord on the document. No progress this week. Steven will check with Stuart Swan on the 11/15 meeting. Steven will consider the synthesis impacts of automatic variables at the named block level. Gord will query the VCS team on the impacts of SV-BC18c. Issues: SV-BC18b: Automatic declarations at the module level and initial block level. The agreement is that automatic declarations do not make sense in the module level, $root, or interfaces, but they do have a use in named begin blocks for improving optimization opportunites, explicit re-initialization on each entry to the block and synthesis variable locality (hierarchical access would be disallowed for these variables). Steve's reservation stems from the IEEE limitation of automatic to tasks and functions only because that is a simpler model in defining re-entrancy. Steve will consider synthesis impacts, and we will revisit this next time. SV-BC18c: Variable initialization does not cause events. IEEE compliant code will not simulate correctly in a SystemVerilog compliant simulator because variable initialization will not create events potentially not causing updates to continuous assignments. The VHDL community likes this semantics because initial blocks, etc can assume that the variables have been initialized. If we were to keep this semantic, and to force the evaluation of all continuous assignments, we risk breaking a number of legacy designs. Gord will query the VCS team on potential impacts. Supply0 and supply1 have a transition from x to 0 (or 1) at time 1. Cliff is opposed to taking out the initialization without an event. Gord and Steven are concerned about legacy designs. SV-BC18d: Implicit initialization of large arrays and structs. Add discussion to the automatic discussion in SV-BC18d. Next meeting is in two weeks, on 10/28/02.