RE: [sv-bc] Query related with the use of assignment pattern on LHS.

None of the simulators I have seem to support assignment patterns on the left hand side of an assignment at all.

Shalom 

> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Dhiraj Kumar Prasad
> Sent: Thursday, November 19, 2009 11:35 AM
> To: sv-bc@server.eda.org
> Cc: Surya Pratik Saha; Dhiraj Kumar Prasad
> Subject: [sv-bc] Query related with the use of assignment 
> pattern on LHS.
> 
> Hello,
> 
> I have a query related with used of assignment pattern  on LHS.
> 
> According to LRM P1800.2005,expression can have "( 
> operator_assignment 
> )" and
> 
> operator_assignment ::= variable_lvalue assignment_operator expression
> 
> So does the following testcase is correct ??
> 
> Testcase
> ---------
> 
> module tmp();
> bit a,b,c[1:0];
> 
> initial
>     '{a,b} = (c = '{1'b0, 1'b1} );
> endmodule
> 
> As most of the standard tool's are showing error for this.
> 
> Regards,
> dhiRAj
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.


-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.