RE: [sv-bc] Query related with explicit name port declaration.

I think this is not legal syntax, to specify a data type with an explicit port declaration:

ansi_port_declaration ::=
  [ net_port_header | interface_port_header ] port_identifier { unpacked_dimension }[ = constant_expression ]
| [ variable_port_header ] port_identifier { variable_dimension } [ = constant_expression ]
| [ port_direction ] . port_identifier ( [ expression ] ) 

The BNF seems to allow only the port direction.

Shalom


> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Dhiraj Kumar Prasad
> Sent: Friday, November 13, 2009 11:35 AM
> To: sv-bc@server.eda.org
> Cc: Surya Pratik Saha
> Subject: [sv-bc] Query related with explicit name port declaration.
> 
> Hello,
> 
> I have a query related with  explicit name port declaration.
> 
> For example
> 
> module mod(output logic .P1(r));
>    int  r;
> endmodule
> 
> In above testcases once a type is specified with port then is 
> this(logic 
> here) will be regarded
> as type of  "r" ??
> 
> If yes then does the redefinition of variable "r" should be 
> treated as 
> illegal as the name
> is previously declared.
> 
> If not then what is the significance of specifying explicit data 
> type(logic here) with port .
> 
> Different standard tools are behaving in  different way.
> 
> Regards,
> dhiRAj
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