Re: [sv-bc] Lifetime of variables declared in packages

John,

> In verilog, a design unit is structurally part of the design.
> This would include a top-level module and all modules
> instantiated.  The instantiations would be statements but
> not design units.

Hmmm, that's not what I thought at all.
However, it appears that I should have spoken of "design
element" rather than "design unit".

1800-2005 contains the phrase "design unit" exactly once, in
clause 23.4 (`begin_keywords); it's never defined.  The meaning
in 23.4 is not at all clear from the context.

1364-2005 also contains "design unit" exactly once, without
definition, and again in a very vague context.

However, the same clause in 1800-2005 uses "design element",
again just once and again without definition, but in a
context that makes it clear it's describing the idea I had
in mind - one of the scope-making, library-element-making
things like package, module, interface, program, UDP.
1364-2005 uses "design element" several times, also
without definition, but again evidently with the same
meaning (and, incidentally, carefully including
configurations in the list).  P1800-2009 formalizes this,
properly defining "design element" (clause 3.2).
Unfortunately, "design unit" also appears - just once,
without definition - in P1800-2009 as well; I suspect
that reflects the same error that I made earlier today.

So I'd suggest going for "design element" in place of
the enumerated list that Shalom mentioned.  And we
should perhaps work out just what it is that we mean
by "design unit", or else get rid of the phrase altogether.
--
Jonathan Bromley
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