RE: [sv-bc] Verilog Std Ambiguity

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Tue Oct 13 2009 - 05:13:35 PDT
The current Verilog-XL documentation supports what Steven says. The Verilog-XL Reference says,

"When a continuous assignment whose left-hand side references a vector net or when a vector net declaration assignment includes delays, the following rules determine which delay controls the assignment. 
The following rules also determine the net delay that controls a continuous assignment to an unexpanded vector net.

If the right-hand side lsb remains 1 or becomes 1, then the rising (first) delay is used.
If the right-hand side lsb remains 0 or becomes 0, then the falling (second) delay is used.
If the right-hand side lsb remains z or becomes z, then the turn-off (third) delay is used.
If the right-hand side lsb is an x or becomes an x, then the smallest of the delay values is used."

The LRM text goes back as far as OVI 1.0.

As I mentioned, I remember seeing this issue being documented somewhere, but it was so far back that I don't have a soft copy anymore. I probably have a hard copy somewhere, but it could take me a while to find it.

The text also does not describe what delay to use if less than three delays are specified.

Presumably it works as in Table 28-9 in 28.16 (In 1364-2005, this is Table 7-9 in section 7.14), which also talks about net delays and describes also what delay is used if only 2 delays are specified.

So the entire list of rules could simply be deleted and just referenced to this table.

That leaves only the question of what value is used, whether just the LSB or the entire value, where for "entire value", we would say that the value is 0 if all bits are 0, x if any bit is x, z if any bit is z and none is x, and 1 if any bit is 1 and none are z or x.

Another and logical alternative would have been to calculate the delay on each bit of the vector separately, as in a parallel connection module path in a specify block.

Shalom
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Received on Tue Oct 13 05:26:09 2009

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