Hi, please see Mantis 1034 (http://www.eda.org/svdb/view.php?id=1034). Regards, Shalom ________________________________ From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On Behalf Of Surya Pratik Saha Sent: Wednesday, August 05, 2009 4:49 PM To: sv-bc@eda.org Subject: [sv-bc] Unclear LRM example for type compatibilty Hi, In SV 2009 draft 7a LRM, section 6.22.2 Equivalent types, there is a big example explaining type compatibility rules in SV. It mentions some rule numbers also, but it is not clear which rule it tries to point out. Also the last assignment as given below marked as illegal, but it is not clear why. s1.v5 = s2.v5; // illegal - types from s1 and s2 (rule 4) BTW, none of the standard simulators or synthesis tool fail for the case. I think LRM should correct it. -- Regards Surya -- This message has been scanned for viruses and dangerous content by MailScanner<http://www.mailscanner.info/>, and is believed to be clean. --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Aug 5 07:33:26 2009
This archive was generated by hypermail 2.1.8 : Wed Aug 05 2009 - 07:34:13 PDT