[sv-bc] Query related with default value to ref port.

Hi,

According to LRM P1800.2005,section 12.4.3

"The syntax to declare a default argument in a subroutine is as follows:

subroutine( [ direction ] [ type ] argument = default_value );

The optional direction can be input, inout, or ref (output ports cannot 
specify defaults).

.....
..
When the subroutine is called, arguments with default values can be 
omitted from the call, and the compiler
shall insert their corresponding values.".

So is the following testcase is valid

module tmp(input [5:0] in1, output reg [14:0] out1);

task automatic TASK1(ref bit signed [6:0] in1 = -16, input signed [5:0] in2,
           output signed [14:0] out1);
begin
  in1 = in1 + in2;
  out1 = in1 * in2;
end
endtask

always @(in1)
  TASK1(, in1, out1);

endmodule

As most of the standard simulators are showing error for this.

Regards,
Dhiraj




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