Hi,
In the above mentioned section, there is an exampled as follows:
parameter logic [7:0] My_DataIn = 8'hFF;
module bus_conn (
output logic [7:0] dataout,
input [7:0] datain = My_DataIn);
assign dataout = datain;
endmodule
module bus_connect1 (
output logic [31:0] dataout,
input [ 7:0] datain);
parameter logic [7:0] My_DataIn = 8'h00;
bus_conn bconn0 (dataout[31:24], 8'h0F);
// Constant literal overrides default in bus_conn definition
bus_conn bconn1 (dataout[23:16]);
// Omitted port for datain, default parameter value 8hFF in
// bus_conn used
bus_conn bconn2 (dataout[15:8], My_DataIn);
// The parameter value 8'h00 from the instantiating scope is used
bus_conn
#(My_DataIn = 8'hF0) bconn3 (dataout[7:0]);
// The parameter value in the bus_conn definition is overridden
// to 8'hF0
endmodule
The highlighted portion is wrong both syntactically and semantically.
Module bus_conn does not have any parameter, and to override a
parameter, this type of syntax is not allowed.
Please correct the example. I am filing a Mantis against that. Hope in
the original version of LRM, all those incorrect examples will be
corrected.
--
Regards
Surya
--
This message has been scanned for viruses and
dangerous content by
MailScanner, and is
believed to be clean.
Received on Mon Jun 15 23:02:04 2009