Re: [sv-bc] RE: email ballot: Due 8am PDT Friday, May 1

From: Gordon Vreugdenhil <gordonv_at_.....>
Date: Thu Apr 30 2009 - 21:09:41 PDT
Mark Hartoog wrote:
> 
> SVDB 2477 ___Yes   _X__No
> http://www.eda.org/svdb/view.php?id=2477
> 
> If enum constants are evaluated in a self determined context it will make them
> inconsistent with how expressions are evaluated elsewhere in system verilog.
> 
> parameter [2:0] p = 2'b11 + 2'b01;
> enum [2:0] { A = 2'b11 + 2'b01, B } e;


This is not a legal enum -- you may not use an explicitly
sized value that doesn't match the enum width.

Given that either sizes have to match the enum base or
be unsized, it isn't clear to me the circumstances under
which there is really going to be a difference.

I guess if you have a >32 bit enum base width and then
added two unsized values that the implementation treated
as 32 bits integers (legal) and that caused a 32 bit overflow
you might get a difference.  A bit obscure, but possible.

Gord
-- 
--------------------------------------------------------------------
Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com


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Received on Thu Apr 30 21:10:29 2009

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